From def89745bc054622dd17ae9d34d1fae06fbd1cfd Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 14 Aug 2023 15:06:11 +0800 Subject: [PATCH] arch-riscv: Allow Minor and O3 CPU execute RVV Change-Id: I4780b42c25d349806254b5053fb0da3b6993ca2f --- src/arch/riscv/RiscvCPU.py | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py index 449bf5e7af..1c77045c67 100644 --- a/src/arch/riscv/RiscvCPU.py +++ b/src/arch/riscv/RiscvCPU.py @@ -41,17 +41,6 @@ class RiscvCPU: ArchISA = RiscvISA -class RiscvISANoRVV(RiscvISA): - enable_rvv = False - - -class RiscvCPUNoRVV: - ArchDecoder = RiscvDecoder - ArchMMU = RiscvMMU - ArchInterrupts = RiscvInterrupts - ArchISA = RiscvISANoRVV - - class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU): mmu = RiscvMMU() @@ -64,9 +53,9 @@ class RiscvTimingSimpleCPU(BaseTimingSimpleCPU, RiscvCPU): mmu = RiscvMMU() -class RiscvO3CPU(BaseO3CPU, RiscvCPUNoRVV): +class RiscvO3CPU(BaseO3CPU, RiscvCPU): mmu = RiscvMMU() -class RiscvMinorCPU(BaseMinorCPU, RiscvCPUNoRVV): +class RiscvMinorCPU(BaseMinorCPU, RiscvCPU): mmu = RiscvMMU()