From deb97742c7ada2008ec79aaf1791f7db3c6a2b06 Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Sun, 31 Jan 2010 22:21:01 -0800 Subject: [PATCH] m5: Added PROTOCOL default for regress fix --- build_opts/ALPHA_FS | 1 + build_opts/ALPHA_SE | 1 + build_opts/ARM_FS | 1 + build_opts/ARM_SE | 1 + build_opts/MIPS_FS | 1 + build_opts/MIPS_SE | 3 ++- build_opts/POWER_SE | 1 + build_opts/SPARC_FS | 1 + build_opts/SPARC_SE | 1 + build_opts/X86_FS | 1 + build_opts/X86_SE | 1 + 11 files changed, 12 insertions(+), 1 deletion(-) diff --git a/build_opts/ALPHA_FS b/build_opts/ALPHA_FS index e69cff04b9..3908039d1a 100644 --- a/build_opts/ALPHA_FS +++ b/build_opts/ALPHA_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'alpha' FULL_SYSTEM = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE index dcd8559fc1..b21fec4cbc 100644 --- a/build_opts/ALPHA_SE +++ b/build_opts/ALPHA_SE @@ -1,3 +1,4 @@ FULL_SYSTEM = 0 SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/ARM_FS b/build_opts/ARM_FS index 508bad76eb..9d518142d4 100644 --- a/build_opts/ARM_FS +++ b/build_opts/ARM_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/ARM_SE b/build_opts/ARM_SE index 93770ac80f..5019edb0a3 100644 --- a/build_opts/ARM_SE +++ b/build_opts/ARM_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/MIPS_FS b/build_opts/MIPS_FS index 81d7fd7a19..3e08a2fcd3 100644 --- a/build_opts/MIPS_FS +++ b/build_opts/MIPS_FS @@ -1,2 +1,3 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/MIPS_SE b/build_opts/MIPS_SE index d3e449f423..0855578983 100644 --- a/build_opts/MIPS_SE +++ b/build_opts/MIPS_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 0 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' \ No newline at end of file +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/POWER_SE b/build_opts/POWER_SE index d76ca7180d..13e175ebcd 100644 --- a/build_opts/POWER_SE +++ b/build_opts/POWER_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'power' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS index 7c8bda0ceb..f1dd81481f 100644 --- a/build_opts/SPARC_FS +++ b/build_opts/SPARC_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/SPARC_SE b/build_opts/SPARC_SE index b288d39085..802176bd04 100644 --- a/build_opts/SPARC_SE +++ b/build_opts/SPARC_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example' diff --git a/build_opts/X86_FS b/build_opts/X86_FS index 7cc6847f29..72cba7443a 100644 --- a/build_opts/X86_FS +++ b/build_opts/X86_FS @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff --git a/build_opts/X86_SE b/build_opts/X86_SE index 5913cde1e4..3e372726dd 100644 --- a/build_opts/X86_SE +++ b/build_opts/X86_SE @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example'