diff --git a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
index 779f1b5b25..207b8a0b09 100644
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
@@ -38,10 +38,10 @@
 microcode = '''
 
 def macroop FABS {
-    absfp st(0), st(0)
+    absfp st(0), st(0), SetStatus=True
 };
 
 def macroop FCHS {
-    chsfp st(0), st(0)
+    chsfp st(0), st(0), SetStatus=True
 };
 '''
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index abb6abb727..e6372ba6be 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -365,9 +365,9 @@ let {{
 
     class absfp(FpUnaryOp):
         code = 'FpDestReg = fabs(FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 
     class chsfp(FpUnaryOp):
         code = 'FpDestReg = (-1) * (FpSrcReg1);'
-        flag_code = 'FSW &= (~CC1Bit);'
+        flag_code = 'FSW = FSW & (~CC1Bit);'
 }};