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misc: Run pre-commit run --all-files

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This is reflect the updates made to black when running `pre-commit
autoupdate`.

Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
This commit is contained in:
Bobby R. Bruce
2023-10-09 12:40:48 -07:00
parent 317d2fb5b8
commit ddf6cb88e4
183 changed files with 120 additions and 175 deletions
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1
build_tools/enum_cc.py
View File

@@ -118,7 +118,6 @@ code("} // namespace gem5")
if use_python: if use_python:
name = enum.__name__ name = enum.__name__
enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name
wrapper_name = enum_name if enum.is_class else enum.wrapper_name wrapper_name = enum_name if enum.is_class else enum.wrapper_name

1
build_tools/sim_object_param_struct_cc.py
View File

@@ -88,7 +88,6 @@ ports = sim_object._ports.local
# only include pybind if python is enabled in the build # only include pybind if python is enabled in the build
if use_python: if use_python:
code( code(
"""#include "pybind11/pybind11.h" """#include "pybind11/pybind11.h"
#include "pybind11/stl.h" #include "pybind11/stl.h"

2
configs/common/GPUTLBConfig.py
View File

@@ -36,7 +36,6 @@ from m5.objects import *
def TLB_constructor(options, level, gpu_ctrl=None, full_system=False): def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
if full_system: if full_system:
constructor_call = ( constructor_call = (
"VegaGPUTLB(\ "VegaGPUTLB(\
@@ -71,7 +70,6 @@ def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
def Coalescer_constructor(options, level, full_system): def Coalescer_constructor(options, level, full_system):
if full_system: if full_system:
constructor_call = ( constructor_call = (
"VegaTLBCoalescer(probesPerCycle = \ "VegaTLBCoalescer(probesPerCycle = \

1
configs/common/GPUTLBOptions.py
View File

@@ -29,7 +29,6 @@
def tlb_options(parser): def tlb_options(parser):
# =================================================================== # ===================================================================
# TLB Configuration # TLB Configuration
# =================================================================== # ===================================================================

2
configs/common/HMC.py
View File

@@ -430,7 +430,6 @@ def add_options(parser):
# configure HMC host controller # configure HMC host controller
def config_hmc_host_ctrl(opt, system): def config_hmc_host_ctrl(opt, system):
# create HMC host controller # create HMC host controller
system.hmc_host = SubSystem() system.hmc_host = SubSystem()
@@ -533,7 +532,6 @@ def config_hmc_host_ctrl(opt, system):
# Create an HMC device # Create an HMC device
def config_hmc_dev(opt, system, hmc_host): def config_hmc_dev(opt, system, hmc_host):
# create HMC device # create HMC device
system.hmc_dev = SubSystem() system.hmc_dev = SubSystem()

2
configs/common/ObjectList.py
View File

@@ -164,7 +164,7 @@ class EnumList(ObjectList):
def _add_objects(self): def _add_objects(self):
"""Add all enum values to the ObjectList""" """Add all enum values to the ObjectList"""
self._sub_classes = {} self._sub_classes = {}
for (key, value) in list(self.base_cls.__members__.items()): for key, value in list(self.base_cls.__members__.items()):
# All Enums have a value Num_NAME at the end which we # All Enums have a value Num_NAME at the end which we
# do not want to include # do not want to include
if not key.startswith("Num_"): if not key.startswith("Num_"):

1
configs/common/Simulation.py
View File

@@ -771,7 +771,6 @@ def run(options, root, testsys, cpu_class):
if ( if (
options.take_checkpoints or options.take_simpoint_checkpoints options.take_checkpoints or options.take_simpoint_checkpoints
) and options.checkpoint_restore: ) and options.checkpoint_restore:
if m5.options.outdir: if m5.options.outdir:
cptdir = m5.options.outdir cptdir = m5.options.outdir
else: else:

1
configs/common/cores/arm/HPI.py
View File

@@ -44,6 +44,7 @@ at: http://www.arm.com/ResearchEnablement/SystemModeling
from m5.objects import * from m5.objects import *
# Simple function to allow a string of [01x_] to be converted into a # Simple function to allow a string of [01x_] to be converted into a
# mask and value for use with MinorFUTiming # mask and value for use with MinorFUTiming
def make_implicant(implicant_string): def make_implicant(implicant_string):

1
configs/common/cores/arm/O3_ARM_Etrace.py
View File

@@ -36,6 +36,7 @@
from m5.objects import * from m5.objects import *
from .O3_ARM_v7a import O3_ARM_v7a_3 from .O3_ARM_v7a import O3_ARM_v7a_3
# O3_ARM_v7a_3 adapted to generate elastic traces # O3_ARM_v7a_3 adapted to generate elastic traces
class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3): class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3):
# Make the number of entries in the ROB, LQ and SQ very # Make the number of entries in the ROB, LQ and SQ very

1
configs/common/cores/arm/O3_ARM_v7a.py
View File

@@ -26,6 +26,7 @@
from m5.objects import * from m5.objects import *
# Simple ALU Instructions have a latency of 1 # Simple ALU Instructions have a latency of 1
class O3_ARM_v7a_Simple_Int(FUDesc): class O3_ARM_v7a_Simple_Int(FUDesc):
opList = [OpDesc(opClass="IntAlu", opLat=1)] opList = [OpDesc(opClass="IntAlu", opLat=1)]

1
configs/common/cores/arm/ex5_LITTLE.py
View File

@@ -31,6 +31,7 @@ from m5.objects import *
# ex5 LITTLE core (based on the ARM Cortex-A7) # ex5 LITTLE core (based on the ARM Cortex-A7)
# ----------------------------------------------------------------------- # -----------------------------------------------------------------------
# Simple ALU Instructions have a latency of 3 # Simple ALU Instructions have a latency of 3
class ex5_LITTLE_Simple_Int(MinorDefaultIntFU): class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
opList = [OpDesc(opClass="IntAlu", opLat=4)] opList = [OpDesc(opClass="IntAlu", opLat=4)]

1
configs/common/cores/arm/ex5_big.py
View File

@@ -31,6 +31,7 @@ from m5.objects import *
# ex5 big core (based on the ARM Cortex-A15) # ex5 big core (based on the ARM Cortex-A15)
# ----------------------------------------------------------------------- # -----------------------------------------------------------------------
# Simple ALU Instructions have a latency of 1 # Simple ALU Instructions have a latency of 1
class ex5_big_Simple_Int(FUDesc): class ex5_big_Simple_Int(FUDesc):
opList = [OpDesc(opClass="IntAlu", opLat=1)] opList = [OpDesc(opClass="IntAlu", opLat=1)]

2
configs/deprecated/example/fs.py
View File

@@ -164,7 +164,7 @@ def build_test_system(np):
# assuming that there is just one such port. # assuming that there is just one such port.
test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports
for (i, cpu) in enumerate(test_sys.cpu): for i, cpu in enumerate(test_sys.cpu):
# #
# Tie the cpu ports to the correct ruby system ports # Tie the cpu ports to the correct ruby system ports
# #

2
configs/dist/sw.py vendored
View File

@@ -62,7 +62,7 @@ def build_switch(args):
for i in range(args.dist_size) for i in range(args.dist_size)
] ]
for (i, link) in enumerate(switch.portlink): for i, link in enumerate(switch.portlink):
link.int0 = switch.interface[i] link.int0 = switch.interface[i]
return switch return switch

3
configs/dram/lat_mem_rd.py
View File

@@ -150,6 +150,7 @@ cfg_file = open(cfg_file_name, "w")
burst_size = 64 burst_size = 64
system.cache_line_size = burst_size system.cache_line_size = burst_size
# lazy version to check if an integer is a power of two # lazy version to check if an integer is a power of two
def is_pow2(num): def is_pow2(num):
return num != 0 and ((num & (num - 1)) == 0) return num != 0 and ((num & (num - 1)) == 0)
@@ -177,6 +178,7 @@ iterations = 2
# do not pile up in the system, adjust if needed # do not pile up in the system, adjust if needed
itt = 150 * 1000 itt = 150 * 1000
# for every data point, we create a trace containing a random address # for every data point, we create a trace containing a random address
# sequence, so that we can play back the same sequence for warming and # sequence, so that we can play back the same sequence for warming and
# the actual measurement # the actual measurement
@@ -276,6 +278,7 @@ system.tgen.port = system.monitor.cpu_side_port
# basic to explore some of the options # basic to explore some of the options
from common.Caches import * from common.Caches import *
# a starting point for an L3 cache # a starting point for an L3 cache
class L3Cache(Cache): class L3Cache(Cache):
assoc = 16 assoc = 16

3
configs/example/apu_se.py
View File

@@ -673,6 +673,7 @@ gpu_driver.device = gpu_cmd_proc
shader.dispatcher = dispatcher shader.dispatcher = dispatcher
shader.gpu_cmd_proc = gpu_cmd_proc shader.gpu_cmd_proc = gpu_cmd_proc
# Create and assign the workload Check for rel_path in elements of # Create and assign the workload Check for rel_path in elements of
# base_list using test, returning the first full path that satisfies test # base_list using test, returning the first full path that satisfies test
def find_path(base_list, rel_path, test): def find_path(base_list, rel_path, test):
@@ -756,7 +757,7 @@ if fast_forward:
] ]
# Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator. # Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator.
for (i, cpu) in enumerate(cpu_list): for i, cpu in enumerate(cpu_list):
for j in range(len(cpu)): for j in range(len(cpu)):
cpu.isa[j].vendor_string = "M5 Simulator" cpu.isa[j].vendor_string = "M5 Simulator"

1
configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py
View File

@@ -117,6 +117,7 @@ board.set_workload(
) )
) )
# This generator will dump the stats and exit the simulation loop when the # This generator will dump the stats and exit the simulation loop when the
# simulation region reaches its end. In the case there is a warmup interval, # simulation region reaches its end. In the case there is a warmup interval,
# the simulation stats are reset after the warmup is complete. # the simulation stats are reset after the warmup is complete.

2
configs/example/gem5_library/x86-npb-benchmarks.py
View File

@@ -211,6 +211,7 @@ board.set_kernel_disk_workload(
readfile_contents=command, readfile_contents=command,
) )
# The first exit_event ends with a `workbegin` cause. This means that the # The first exit_event ends with a `workbegin` cause. This means that the
# system started successfully and the execution on the program started. # system started successfully and the execution on the program started.
def handle_workbegin(): def handle_workbegin():
@@ -236,6 +237,7 @@ def handle_workbegin():
# The next exit_event is to simulate the ROI. It should be exited with a cause # The next exit_event is to simulate the ROI. It should be exited with a cause
# marked by `workend`. # marked by `workend`.
# We exepect that ROI ends with `workend` or `simulate() limit reached`. # We exepect that ROI ends with `workend` or `simulate() limit reached`.
def handle_workend(): def handle_workend():
print("Dump stats at the end of the ROI!") print("Dump stats at the end of the ROI!")

1
configs/example/gem5_library/x86-parsec-benchmarks.py
View File

@@ -192,6 +192,7 @@ board.set_kernel_disk_workload(
readfile_contents=command, readfile_contents=command,
) )
# functions to handle different exit events during the simuation # functions to handle different exit events during the simuation
def handle_workbegin(): def handle_workbegin():
print("Done booting Linux") print("Done booting Linux")

5
configs/example/gpufs/DisjointNetwork.py
View File

@@ -46,7 +46,6 @@ class DisjointSimple(SimpleNetwork):
self.ruby_system = ruby_system self.ruby_system = ruby_system
def connectCPU(self, opts, controllers): def connectCPU(self, opts, controllers):
# Setup parameters for makeTopology call for CPU network # Setup parameters for makeTopology call for CPU network
topo_module = import_module(f"topologies.{opts.cpu_topology}") topo_module = import_module(f"topologies.{opts.cpu_topology}")
topo_class = getattr(topo_module, opts.cpu_topology) topo_class = getattr(topo_module, opts.cpu_topology)
@@ -56,7 +55,6 @@ class DisjointSimple(SimpleNetwork):
self.initSimple(opts, self.int_links, self.ext_links) self.initSimple(opts, self.int_links, self.ext_links)
def connectGPU(self, opts, controllers): def connectGPU(self, opts, controllers):
# Setup parameters for makeTopology call for GPU network # Setup parameters for makeTopology call for GPU network
topo_module = import_module(f"topologies.{opts.gpu_topology}") topo_module = import_module(f"topologies.{opts.gpu_topology}")
topo_class = getattr(topo_module, opts.gpu_topology) topo_class = getattr(topo_module, opts.gpu_topology)
@@ -66,7 +64,6 @@ class DisjointSimple(SimpleNetwork):
self.initSimple(opts, self.int_links, self.ext_links) self.initSimple(opts, self.int_links, self.ext_links)
def initSimple(self, opts, int_links, ext_links): def initSimple(self, opts, int_links, ext_links):
# Attach links to network # Attach links to network
self.int_links = int_links self.int_links = int_links
self.ext_links = ext_links self.ext_links = ext_links
@@ -82,7 +79,6 @@ class DisjointGarnet(GarnetNetwork):
self.ruby_system = ruby_system self.ruby_system = ruby_system
def connectCPU(self, opts, controllers): def connectCPU(self, opts, controllers):
# Setup parameters for makeTopology call for CPU network # Setup parameters for makeTopology call for CPU network
topo_module = import_module(f"topologies.{opts.cpu_topology}") topo_module = import_module(f"topologies.{opts.cpu_topology}")
topo_class = getattr(topo_module, opts.cpu_topology) topo_class = getattr(topo_module, opts.cpu_topology)
@@ -94,7 +90,6 @@ class DisjointGarnet(GarnetNetwork):
Network.init_network(opts, self, GarnetNetworkInterface) Network.init_network(opts, self, GarnetNetworkInterface)
def connectGPU(self, opts, controllers): def connectGPU(self, opts, controllers):
# Setup parameters for makeTopology call # Setup parameters for makeTopology call
topo_module = import_module(f"topologies.{opts.gpu_topology}") topo_module = import_module(f"topologies.{opts.gpu_topology}")
topo_class = getattr(topo_module, opts.gpu_topology) topo_class = getattr(topo_module, opts.gpu_topology)

2
configs/example/gpufs/Disjoint_VIPER.py
View File

@@ -38,7 +38,6 @@ from ruby import Ruby
class DummySystem: class DummySystem:
def __init__(self, mem_ranges): def __init__(self, mem_ranges):
self.mem_ctrls = [] self.mem_ctrls = []
self.mem_ranges = mem_ranges self.mem_ranges = mem_ranges
@@ -51,7 +50,6 @@ class Disjoint_VIPER(RubySystem):
super(Disjoint_VIPER, self).__init__() super(Disjoint_VIPER, self).__init__()
def create(self, options, system, piobus, dma_devices): def create(self, options, system, piobus, dma_devices):
# Disjoint network topology # Disjoint network topology
if "garnet" in options.network: if "garnet" in options.network:
self.network_cpu = DisjointGarnet(self) self.network_cpu = DisjointGarnet(self)

2
configs/example/gpufs/system/system.py
View File

@@ -267,7 +267,7 @@ def makeGpuFSSystem(args):
# and FMA. # and FMA.
avx_cpu_features = [0x00020F51, 0x00000805, 0xEFDBFBFF, 0x1C983209] avx_cpu_features = [0x00020F51, 0x00000805, 0xEFDBFBFF, 0x1C983209]
for (i, cpu) in enumerate(system.cpu): for i, cpu in enumerate(system.cpu):
# Break once we reach the shader "CPU" # Break once we reach the shader "CPU"
if i == args.num_cpus: if i == args.num_cpus:
break break

1
configs/example/memcheck.py
View File

@@ -260,6 +260,7 @@ system.memchecker = MemChecker()
# For each level, track the next subsys index to use # For each level, track the next subsys index to use
next_subsys_index = [0] * (len(cachespec) + 1) next_subsys_index = [0] * (len(cachespec) + 1)
# Recursive function to create a sub-tree of the cache and tester # Recursive function to create a sub-tree of the cache and tester
# hierarchy # hierarchy
def make_cache_level(ncaches, prototypes, level, next_cache): def make_cache_level(ncaches, prototypes, level, next_cache):

2
configs/example/memtest.py
View File

@@ -145,6 +145,7 @@ parser.add_argument(
args = parser.parse_args() args = parser.parse_args()
# Get the total number of testers # Get the total number of testers
def numtesters(cachespec, testerspec): def numtesters(cachespec, testerspec):
# Determine the tester multiplier for each level as the # Determine the tester multiplier for each level as the
@@ -278,6 +279,7 @@ system.clk_domain = SrcClockDomain(
# For each level, track the next subsys index to use # For each level, track the next subsys index to use
next_subsys_index = [0] * (len(cachespec) + 1) next_subsys_index = [0] * (len(cachespec) + 1)
# Recursive function to create a sub-tree of the cache and tester # Recursive function to create a sub-tree of the cache and tester
# hierarchy # hierarchy
def make_cache_level(ncaches, prototypes, level, next_cache): def make_cache_level(ncaches, prototypes, level, next_cache):

1
configs/example/noc_config/2x4.py
View File

@@ -35,6 +35,7 @@
from ruby import CHI_config from ruby import CHI_config
# CustomMesh parameters for a 2x4 mesh. Routers will have the following layout: # CustomMesh parameters for a 2x4 mesh. Routers will have the following layout:
# #
# 0 --- 1 --- 2 --- 3 # 0 --- 1 --- 2 --- 3

1
configs/example/read_config.py
View File

@@ -366,7 +366,6 @@ class ConfigManager(object):
if port_has_correct_index(from_port) and port_has_correct_index( if port_has_correct_index(from_port) and port_has_correct_index(
to_port to_port
): ):
connections_to_make.append((from_port, to_port)) connections_to_make.append((from_port, to_port))
increment_port_index(from_port) increment_port_index(from_port)

2
configs/learning_gem5/part3/msi_caches.py
View File

@@ -110,7 +110,6 @@ class MyCacheSystem(RubySystem):
class L1Cache(L1Cache_Controller): class L1Cache(L1Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod
@@ -174,7 +173,6 @@ class L1Cache(L1Cache_Controller):
class DirController(Directory_Controller): class DirController(Directory_Controller):
_version = 0 _version = 0
@classmethod @classmethod

2
configs/learning_gem5/part3/ruby_caches_MI_example.py
View File

@@ -108,7 +108,6 @@ class MyCacheSystem(RubySystem):
class L1Cache(L1Cache_Controller): class L1Cache(L1Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod
@@ -163,7 +162,6 @@ class L1Cache(L1Cache_Controller):
class DirController(Directory_Controller): class DirController(Directory_Controller):
_version = 0 _version = 0
@classmethod @classmethod

2
configs/network/Network.py
View File

@@ -121,7 +121,6 @@ def define_options(parser):
def create_network(options, ruby): def create_network(options, ruby):
# Allow legacy users to use garnet through garnet2.0 option # Allow legacy users to use garnet through garnet2.0 option
# until next gem5 release. # until next gem5 release.
if options.network == "garnet2.0": if options.network == "garnet2.0":
@@ -162,7 +161,6 @@ def create_network(options, ruby):
def init_network(options, network, InterfaceClass): def init_network(options, network, InterfaceClass):
if options.network == "garnet": if options.network == "garnet":
network.num_rows = options.mesh_rows network.num_rows = options.mesh_rows
network.vcs_per_vnet = options.vcs_per_vnet network.vcs_per_vnet = options.vcs_per_vnet

2
configs/ruby/AMD_Base_Constructor.py
View File

@@ -38,6 +38,7 @@ addToPath("../")
from topologies.Cluster import Cluster from topologies.Cluster import Cluster
# #
# Note: the L1 Cache latency is only used by the sequencer on fast path hits # Note: the L1 Cache latency is only used by the sequencer on fast path hits
# #
@@ -115,7 +116,6 @@ def construct(options, system, ruby_system):
cpuCluster = None cpuCluster = None
cpuCluster = Cluster(name="CPU Cluster", extBW=8, intBW=8) # 16 GB/s cpuCluster = Cluster(name="CPU Cluster", extBW=8, intBW=8) # 16 GB/s
for i in range((options.num_cpus + 1) // 2): for i in range((options.num_cpus + 1) // 2):
cp_cntrl = CPCntrl() cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system) cp_cntrl.create(options, ruby_system, system)

1
configs/ruby/CHI.py
View File

@@ -65,7 +65,6 @@ def read_config_file(file):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "CHI": if buildEnv["PROTOCOL"] != "CHI":
m5.panic("This script requires the CHI build") m5.panic("This script requires the CHI build")

13
configs/ruby/GPU_VIPER.py
View File

@@ -524,7 +524,6 @@ def define_options(parser):
def construct_dirs(options, system, ruby_system, network): def construct_dirs(options, system, ruby_system, network):
dir_cntrl_nodes = [] dir_cntrl_nodes = []
# For an odd number of CPUs, still create the right number of controllers # For an odd number of CPUs, still create the right number of controllers
@@ -592,7 +591,6 @@ def construct_dirs(options, system, ruby_system, network):
def construct_gpudirs(options, system, ruby_system, network): def construct_gpudirs(options, system, ruby_system, network):
dir_cntrl_nodes = [] dir_cntrl_nodes = []
mem_ctrls = [] mem_ctrls = []
@@ -681,12 +679,10 @@ def construct_gpudirs(options, system, ruby_system, network):
def construct_corepairs(options, system, ruby_system, network): def construct_corepairs(options, system, ruby_system, network):
cpu_sequencers = [] cpu_sequencers = []
cp_cntrl_nodes = [] cp_cntrl_nodes = []
for i in range((options.num_cpus + 1) // 2): for i in range((options.num_cpus + 1) // 2):
cp_cntrl = CPCntrl() cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system) cp_cntrl.create(options, ruby_system, system)
@@ -721,7 +717,6 @@ def construct_corepairs(options, system, ruby_system, network):
def construct_tcps(options, system, ruby_system, network): def construct_tcps(options, system, ruby_system, network):
tcp_sequencers = [] tcp_sequencers = []
tcp_cntrl_nodes = [] tcp_cntrl_nodes = []
@@ -729,7 +724,6 @@ def construct_tcps(options, system, ruby_system, network):
TCC_bits = int(math.log(options.num_tccs, 2)) TCC_bits = int(math.log(options.num_tccs, 2))
for i in range(options.num_compute_units): for i in range(options.num_compute_units):
tcp_cntrl = TCPCntrl( tcp_cntrl = TCPCntrl(
TCC_select_num_bits=TCC_bits, issue_latency=1, number_of_TBEs=2560 TCC_select_num_bits=TCC_bits, issue_latency=1, number_of_TBEs=2560
) )
@@ -769,7 +763,6 @@ def construct_tcps(options, system, ruby_system, network):
def construct_sqcs(options, system, ruby_system, network): def construct_sqcs(options, system, ruby_system, network):
sqc_sequencers = [] sqc_sequencers = []
sqc_cntrl_nodes = [] sqc_cntrl_nodes = []
@@ -777,7 +770,6 @@ def construct_sqcs(options, system, ruby_system, network):
TCC_bits = int(math.log(options.num_tccs, 2)) TCC_bits = int(math.log(options.num_tccs, 2))
for i in range(options.num_sqc): for i in range(options.num_sqc):
sqc_cntrl = SQCCntrl(TCC_select_num_bits=TCC_bits) sqc_cntrl = SQCCntrl(TCC_select_num_bits=TCC_bits)
sqc_cntrl.create(options, ruby_system, system) sqc_cntrl.create(options, ruby_system, system)
@@ -804,7 +796,6 @@ def construct_sqcs(options, system, ruby_system, network):
def construct_scalars(options, system, ruby_system, network): def construct_scalars(options, system, ruby_system, network):
scalar_sequencers = [] scalar_sequencers = []
scalar_cntrl_nodes = [] scalar_cntrl_nodes = []
@@ -837,7 +828,6 @@ def construct_scalars(options, system, ruby_system, network):
def construct_cmdprocs(options, system, ruby_system, network): def construct_cmdprocs(options, system, ruby_system, network):
cmdproc_sequencers = [] cmdproc_sequencers = []
cmdproc_cntrl_nodes = [] cmdproc_cntrl_nodes = []
@@ -845,7 +835,6 @@ def construct_cmdprocs(options, system, ruby_system, network):
TCC_bits = int(math.log(options.num_tccs, 2)) TCC_bits = int(math.log(options.num_tccs, 2))
for i in range(options.num_cp): for i in range(options.num_cp):
tcp_ID = options.num_compute_units + i tcp_ID = options.num_compute_units + i
sqc_ID = options.num_sqc + i sqc_ID = options.num_sqc + i
@@ -898,11 +887,9 @@ def construct_cmdprocs(options, system, ruby_system, network):
def construct_tccs(options, system, ruby_system, network): def construct_tccs(options, system, ruby_system, network):
tcc_cntrl_nodes = [] tcc_cntrl_nodes = []
for i in range(options.num_tccs): for i in range(options.num_tccs):
tcc_cntrl = TCCCntrl(l2_response_latency=options.TCC_latency) tcc_cntrl = TCCCntrl(l2_response_latency=options.TCC_latency)
tcc_cntrl.create(options, ruby_system, system) tcc_cntrl.create(options, ruby_system, system)
tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency

1
configs/ruby/Garnet_standalone.py
View File

@@ -31,6 +31,7 @@ from m5.defines import buildEnv
from m5.util import addToPath from m5.util import addToPath
from .Ruby import create_topology, create_directories from .Ruby import create_topology, create_directories
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #

2
configs/ruby/MESI_Three_Level.py
View File

@@ -35,6 +35,7 @@ from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
from common import FileSystemConfig from common import FileSystemConfig
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -77,7 +78,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MESI_Three_Level": if buildEnv["PROTOCOL"] != "MESI_Three_Level":
fatal( fatal(
"This script requires the MESI_Three_Level protocol to be\ "This script requires the MESI_Three_Level protocol to be\

2
configs/ruby/MESI_Three_Level_HTM.py
View File

@@ -35,6 +35,7 @@ from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
from common import FileSystemConfig from common import FileSystemConfig
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -77,7 +78,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MESI_Three_Level_HTM": if buildEnv["PROTOCOL"] != "MESI_Three_Level_HTM":
fatal( fatal(
"This script requires the MESI_Three_Level protocol to be\ "This script requires the MESI_Three_Level protocol to be\

2
configs/ruby/MESI_Two_Level.py
View File

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
from .Ruby import create_topology, create_directories from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -50,7 +51,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MESI_Two_Level": if buildEnv["PROTOCOL"] != "MESI_Two_Level":
fatal("This script requires the MESI_Two_Level protocol to be built.") fatal("This script requires the MESI_Two_Level protocol to be built.")

2
configs/ruby/MI_example.py
View File

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
from .Ruby import create_topology, create_directories from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -46,7 +47,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MI_example": if buildEnv["PROTOCOL"] != "MI_example":
panic("This script requires the MI_example protocol to be built.") panic("This script requires the MI_example protocol to be built.")

1
configs/ruby/MOESI_AMD_Base.py
View File

@@ -327,7 +327,6 @@ def create_system(
# For an odd number of CPUs, still create the right number of controllers # For an odd number of CPUs, still create the right number of controllers
cpuCluster = Cluster(extBW=512, intBW=512) # 1 TB/s cpuCluster = Cluster(extBW=512, intBW=512) # 1 TB/s
for i in range((options.num_cpus + 1) // 2): for i in range((options.num_cpus + 1) // 2):
cp_cntrl = CPCntrl() cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system) cp_cntrl.create(options, ruby_system, system)

2
configs/ruby/MOESI_CMP_directory.py
View File

@@ -44,6 +44,7 @@ from m5.defines import buildEnv
from .Ruby import create_topology, create_directories from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -64,7 +65,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MOESI_CMP_directory": if buildEnv["PROTOCOL"] != "MOESI_CMP_directory":
panic( panic(
"This script requires the MOESI_CMP_directory protocol to be built." "This script requires the MOESI_CMP_directory protocol to be built."

2
configs/ruby/MOESI_CMP_token.py
View File

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
from .Ruby import create_topology, create_directories from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -71,7 +72,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MOESI_CMP_token": if buildEnv["PROTOCOL"] != "MOESI_CMP_token":
panic("This script requires the MOESI_CMP_token protocol to be built.") panic("This script requires the MOESI_CMP_token protocol to be built.")

2
configs/ruby/MOESI_hammer.py
View File

@@ -33,6 +33,7 @@ from .Ruby import create_topology, create_directories
from .Ruby import send_evicts from .Ruby import send_evicts
from common import FileSystemConfig from common import FileSystemConfig
# #
# Declare caches used by the protocol # Declare caches used by the protocol
# #
@@ -70,7 +71,6 @@ def define_options(parser):
def create_system( def create_system(
options, full_system, system, dma_ports, bootmem, ruby_system, cpus options, full_system, system, dma_ports, bootmem, ruby_system, cpus
): ):
if buildEnv["PROTOCOL"] != "MOESI_hammer": if buildEnv["PROTOCOL"] != "MOESI_hammer":
panic("This script requires the MOESI_hammer protocol to be built.") panic("This script requires the MOESI_hammer protocol to be built.")

1
configs/ruby/Ruby.py
View File

@@ -221,7 +221,6 @@ def create_system(
bootmem=None, bootmem=None,
cpus=None, cpus=None,
): ):
system.ruby = RubySystem() system.ruby = RubySystem()
ruby = system.ruby ruby = system.ruby

1
configs/splash2/cluster.py
View File

@@ -64,6 +64,7 @@ parser.add_argument("-b", "--benchmark", help="Splash 2 benchmark to run")
args = parser.parse_args() args = parser.parse_args()
# -------------------- # --------------------
# Define Splash2 Benchmarks # Define Splash2 Benchmarks
# ==================== # ====================

1
configs/splash2/run.py
View File

@@ -66,6 +66,7 @@ if not args.numcpus:
print("Specify the number of cpus with -n") print("Specify the number of cpus with -n")
sys.exit(1) sys.exit(1)
# -------------------- # --------------------
# Define Splash2 Benchmarks # Define Splash2 Benchmarks
# ==================== # ====================

1
configs/topologies/Crossbar.py
View File

@@ -34,7 +34,6 @@ class Crossbar(SimpleTopology):
description = "Crossbar" description = "Crossbar"
def makeTopology(self, options, network, IntLink, ExtLink, Router): def makeTopology(self, options, network, IntLink, ExtLink, Router):
# default values for link latency and router latency. # default values for link latency and router latency.
# Can be over-ridden on a per link/router basis # Can be over-ridden on a per link/router basis
link_latency = options.link_latency # used by simple and garnet link_latency = options.link_latency # used by simple and garnet

1
configs/topologies/CustomMesh.py
View File

@@ -67,7 +67,6 @@ class CustomMesh(SimpleTopology):
cross_links, cross_links,
cross_link_latency, cross_link_latency,
): ):
# East->West, West->East, North->South, South->North # East->West, West->East, North->South, South->North
# XY routing weights # XY routing weights
link_weights = [1, 1, 2, 2] link_weights = [1, 1, 2, 2]

4
configs/topologies/MeshDirCorners_XY.py
View File

@@ -91,7 +91,7 @@ class MeshDirCorners_XY(SimpleTopology):
# Connect each cache controller to the appropriate router # Connect each cache controller to the appropriate router
ext_links = [] ext_links = []
for (i, n) in enumerate(cache_nodes): for i, n in enumerate(cache_nodes):
cntrl_level, router_id = divmod(i, num_routers) cntrl_level, router_id = divmod(i, num_routers)
assert cntrl_level < caches_per_router assert cntrl_level < caches_per_router
ext_links.append( ext_links.append(
@@ -161,7 +161,7 @@ class MeshDirCorners_XY(SimpleTopology):
link_count += 1 link_count += 1
# Connect the dma nodes to router 0. These should only be DMA nodes. # Connect the dma nodes to router 0. These should only be DMA nodes.
for (i, node) in enumerate(dma_nodes): for i, node in enumerate(dma_nodes):
assert node.type == "DMA_Controller" assert node.type == "DMA_Controller"
ext_links.append( ext_links.append(
ExtLink( ExtLink(

4
configs/topologies/Mesh_XY.py
View File

@@ -87,7 +87,7 @@ class Mesh_XY(SimpleTopology):
# Connect each node to the appropriate router # Connect each node to the appropriate router
ext_links = [] ext_links = []
for (i, n) in enumerate(network_nodes): for i, n in enumerate(network_nodes):
cntrl_level, router_id = divmod(i, num_routers) cntrl_level, router_id = divmod(i, num_routers)
assert cntrl_level < cntrls_per_router assert cntrl_level < cntrls_per_router
ext_links.append( ext_links.append(
@@ -102,7 +102,7 @@ class Mesh_XY(SimpleTopology):
# Connect the remainding nodes to router 0. These should only be # Connect the remainding nodes to router 0. These should only be
# DMA nodes. # DMA nodes.
for (i, node) in enumerate(remainder_nodes): for i, node in enumerate(remainder_nodes):
assert node.type == "DMA_Controller" assert node.type == "DMA_Controller"
assert i < remainder assert i < remainder
ext_links.append( ext_links.append(

4
configs/topologies/Mesh_westfirst.py
View File

@@ -90,7 +90,7 @@ class Mesh_westfirst(SimpleTopology):
# Connect each node to the appropriate router # Connect each node to the appropriate router
ext_links = [] ext_links = []
for (i, n) in enumerate(network_nodes): for i, n in enumerate(network_nodes):
cntrl_level, router_id = divmod(i, num_routers) cntrl_level, router_id = divmod(i, num_routers)
assert cntrl_level < cntrls_per_router assert cntrl_level < cntrls_per_router
ext_links.append( ext_links.append(
@@ -105,7 +105,7 @@ class Mesh_westfirst(SimpleTopology):
# Connect the remainding nodes to router 0. These should only be # Connect the remainding nodes to router 0. These should only be
# DMA nodes. # DMA nodes.
for (i, node) in enumerate(remainder_nodes): for i, node in enumerate(remainder_nodes):
assert node.type == "DMA_Controller" assert node.type == "DMA_Controller"
assert i < remainder assert i < remainder
ext_links.append( ext_links.append(

1
ext/testlib/helper.py
View File

@@ -132,6 +132,7 @@ class TimedWaitPID(object):
# Patch os.waitpid() # Patch os.waitpid()
TimedWaitPID.install() TimedWaitPID.install()
# TODO Tear out duplicate logic from the sandbox IOManager # TODO Tear out duplicate logic from the sandbox IOManager
def log_call(logger, command, time, *popenargs, **kwargs): def log_call(logger, command, time, *popenargs, **kwargs):
""" """

1
ext/testlib/query.py
View File

@@ -29,6 +29,7 @@
import testlib.terminal as terminal import testlib.terminal as terminal
import testlib.log as log import testlib.log as log
# TODO Refactor print logic out of this so the objects # TODO Refactor print logic out of this so the objects
# created are separate from print logic. # created are separate from print logic.
class QueryRunner(object): class QueryRunner(object):

1
src/arch/arm/ArmISA.py
View File

@@ -41,6 +41,7 @@ from m5.objects.ArmPMU import ArmPMU
from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease
from m5.objects.BaseISA import BaseISA from m5.objects.BaseISA import BaseISA
# Enum for DecoderFlavor # Enum for DecoderFlavor
class DecoderFlavor(Enum): class DecoderFlavor(Enum):
vals = ["Generic"] vals = ["Generic"]

1
src/arch/arm/ArmMMU.py
View File

@@ -42,6 +42,7 @@ from m5.objects.ClockedObject import ClockedObject
from m5.params import * from m5.params import *
from m5.proxy import * from m5.proxy import *
# Basic stage 1 translation objects # Basic stage 1 translation objects
class ArmTableWalker(ClockedObject): class ArmTableWalker(ClockedObject):
type = "ArmTableWalker" type = "ArmTableWalker"

1
src/arch/isa_parser/isa_parser.py
View File

@@ -374,6 +374,7 @@ def substBitOps(code):
# #
##################################################################### #####################################################################
# Force the argument to be a list. Useful for flags, where a caller # Force the argument to be a list. Useful for flags, where a caller
# can specify a singleton flag or a list of flags. Also usful for # can specify a singleton flag or a list of flags. Also usful for
# converting tuples to lists so they can be modified. # converting tuples to lists so they can be modified.

1
src/arch/isa_parser/operand_types.py
View File

@@ -50,7 +50,6 @@ class OperandDesc(object):
def __init__( def __init__(
self, base_cls, dflt_ext, reg_spec, flags=None, sort_pri=None self, base_cls, dflt_ext, reg_spec, flags=None, sort_pri=None
): ):
from .isa_parser import makeList from .isa_parser import makeList
# Canonical flag structure is a triple of lists, where each list # Canonical flag structure is a triple of lists, where each list

1
src/arch/isa_parser/util.py
View File

@@ -42,6 +42,7 @@ import re
################### ###################
# Utility functions # Utility functions
# #
# Indent every line in string 's' by two spaces # Indent every line in string 's' by two spaces
# (except preprocessor directives). # (except preprocessor directives).

3
src/arch/micro_asm.py
View File

@@ -187,6 +187,7 @@ def handle_statement(parser, container, statement):
# #
########################################################################## ##########################################################################
# Error handler. Just call exit. Output formatted to work under # Error handler. Just call exit. Output formatted to work under
# Emacs compile-mode. Optional 'print_traceback' arg, if set to True, # Emacs compile-mode. Optional 'print_traceback' arg, if set to True,
# prints a Python stack backtrace too (can be handy when trying to # prints a Python stack backtrace too (can be handy when trying to
@@ -231,6 +232,7 @@ reserved_map = {}
for r in reserved: for r in reserved:
reserved_map[r.lower()] = r reserved_map[r.lower()] = r
# Ignore comments # Ignore comments
def t_ANY_COMMENT(t): def t_ANY_COMMENT(t):
r"\#[^\n]*(?=\n)" r"\#[^\n]*(?=\n)"
@@ -360,6 +362,7 @@ def t_ANY_error(t):
# #
########################################################################## ##########################################################################
# Start symbol for a file which may have more than one macroop or rom # Start symbol for a file which may have more than one macroop or rom
# specification. # specification.
def p_file(t): def p_file(t):

1
src/arch/x86/bios/ACPI.py
View File

@@ -36,6 +36,7 @@
from m5.params import * from m5.params import *
from m5.SimObject import SimObject from m5.SimObject import SimObject
# ACPI description table header. Subclasses contain and handle the actual # ACPI description table header. Subclasses contain and handle the actual
# contents as appropriate for that type of table. # contents as appropriate for that type of table.
class X86ACPISysDescTable(SimObject): class X86ACPISysDescTable(SimObject):

1
src/base/Graphics.py
View File

@@ -36,6 +36,7 @@
from m5.SimObject import SimObject from m5.SimObject import SimObject
from m5.params import * from m5.params import *
# Image Formats: # Image Formats:
# Auto option will let gem5 to choose the image format it prefers. # Auto option will let gem5 to choose the image format it prefers.
class ImageFormat(Enum): class ImageFormat(Enum):

1
src/cpu/testers/traffic_gen/BaseTrafficGen.py
View File

@@ -37,6 +37,7 @@ from m5.params import *
from m5.proxy import * from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject from m5.objects.ClockedObject import ClockedObject
# Types of Stream Generators. # Types of Stream Generators.
# Those are orthogonal to the other generators in the TrafficGen # Those are orthogonal to the other generators in the TrafficGen
# and are meant to initialize the stream and substream IDs for # and are meant to initialize the stream and substream IDs for

1
src/cpu/testers/traffic_gen/TrafficGen.py
View File

@@ -36,6 +36,7 @@
from m5.params import * from m5.params import *
from m5.objects.BaseTrafficGen import * from m5.objects.BaseTrafficGen import *
# The behaviour of this traffic generator is specified in a # The behaviour of this traffic generator is specified in a
# configuration file, and this file describes a state transition graph # configuration file, and this file describes a state transition graph
# where each state is a specific generator behaviour. Examples include # where each state is a specific generator behaviour. Examples include

1
src/dev/IntPin.py
View File

@@ -29,6 +29,7 @@ INT_SOURCE_ROLE = "Int Source Pin"
INT_SINK_ROLE = "Int Sink Pin" INT_SINK_ROLE = "Int Sink Pin"
Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE) Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
# A source pin generally represents a single pin which might connect to # A source pin generally represents a single pin which might connect to
# multiple sinks. # multiple sinks.
class IntSourcePin(VectorPort): class IntSourcePin(VectorPort):

1
src/dev/ResetPort.py
View File

@@ -29,6 +29,7 @@ RESET_REQUEST_ROLE = "Reset Request"
RESET_RESPONSE_ROLE = "Reset Response" RESET_RESPONSE_ROLE = "Reset Response"
Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE) Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE)
# ResetRequestPort is an artifact request port for reset purpose. # ResetRequestPort is an artifact request port for reset purpose.
class ResetRequestPort(Port): class ResetRequestPort(Port):
def __init__(self, desc): def __init__(self, desc):

1
src/dev/amdgpu/AMDGPU.py
View File

@@ -34,6 +34,7 @@ from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
from m5.objects.Device import DmaDevice, DmaVirtDevice from m5.objects.Device import DmaDevice, DmaVirtDevice
from m5.objects.ClockedObject import ClockedObject from m5.objects.ClockedObject import ClockedObject
# PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs # PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
# correspond to a Vega Frontier Edition hardware device. None of the PCI # correspond to a Vega Frontier Edition hardware device. None of the PCI
# related values in this class should be changed. # related values in this class should be changed.

1
src/dev/arm/FlashDevice.py
View File

@@ -38,6 +38,7 @@ from m5.proxy import *
from m5.objects.AbstractNVM import * from m5.objects.AbstractNVM import *
# Distribution of the data. # Distribution of the data.
# sequential: sequential (address n+1 is likely to be on the same plane as n) # sequential: sequential (address n+1 is likely to be on the same plane as n)
# Random: @TODO Not yet implemented # Random: @TODO Not yet implemented

1
src/dev/lupio/LupioBLK.py
View File

@@ -31,7 +31,6 @@ from m5.proxy import Parent
class LupioBLK(DmaDevice): class LupioBLK(DmaDevice):
type = "LupioBLK" type = "LupioBLK"
cxx_class = "gem5::LupioBLK" cxx_class = "gem5::LupioBLK"
cxx_header = "dev/lupio/lupio_blk.hh" cxx_header = "dev/lupio/lupio_blk.hh"

1
src/dev/lupio/LupioPIC.py
View File

@@ -29,7 +29,6 @@ from m5.params import Param
class LupioPIC(BasicPioDevice): class LupioPIC(BasicPioDevice):
type = "LupioPIC" type = "LupioPIC"
cxx_class = "gem5::LupioPIC" cxx_class = "gem5::LupioPIC"
cxx_header = "dev/lupio/lupio_pic.hh" cxx_header = "dev/lupio/lupio_pic.hh"

1
src/dev/lupio/LupioRNG.py
View File

@@ -30,7 +30,6 @@ from m5.proxy import Parent
class LupioRNG(BasicPioDevice): class LupioRNG(BasicPioDevice):
type = "LupioRNG" type = "LupioRNG"
cxx_class = "gem5::LupioRNG" cxx_class = "gem5::LupioRNG"
cxx_header = "dev/lupio/lupio_rng.hh" cxx_header = "dev/lupio/lupio_rng.hh"

1
src/dev/pci/PciHost.py
View File

@@ -76,7 +76,6 @@ class GenericPciHost(PciHost):
relocatable=0, relocatable=0,
addr=0, addr=0,
): ):
busf = bus & 0xFF busf = bus & 0xFF
devicef = device & 0x1F devicef = device & 0x1F
functionf = function & 0x7 functionf = function & 0x7

1
src/dev/sparc/T1000.py
View File

@@ -151,6 +151,7 @@ class T1000(Platform):
puart0 = Uart8250(pio_addr=0x1F10000000) puart0 = Uart8250(pio_addr=0x1F10000000)
iob = Iob() iob = Iob()
# Attach I/O devices that are on chip # Attach I/O devices that are on chip
def attachOnChipIO(self, bus): def attachOnChipIO(self, bus):
self.iob.pio = bus.mem_side_ports self.iob.pio = bus.mem_side_ports

1
src/mem/AddrMapper.py
View File

@@ -36,6 +36,7 @@
from m5.params import * from m5.params import *
from m5.SimObject import SimObject from m5.SimObject import SimObject
# An address mapper changes the packet addresses in going from the # An address mapper changes the packet addresses in going from the
# response port side of the mapper to the request port side. When the # response port side of the mapper to the request port side. When the
# response port is queried for the address ranges, it also performs the # response port is queried for the address ranges, it also performs the

1
src/mem/CommMonitor.py
View File

@@ -38,6 +38,7 @@ from m5.proxy import *
from m5.objects.System import System from m5.objects.System import System
from m5.SimObject import SimObject from m5.SimObject import SimObject
# The communication monitor will most typically be used in combination # The communication monitor will most typically be used in combination
# with periodic dumping and resetting of stats using schedStatEvent # with periodic dumping and resetting of stats using schedStatEvent
class CommMonitor(SimObject): class CommMonitor(SimObject):

1
src/mem/DRAMSim2.py
View File

@@ -38,6 +38,7 @@ from citations import add_citation
from m5.params import * from m5.params import *
from m5.objects.AbstractMemory import * from m5.objects.AbstractMemory import *
# A wrapper for DRAMSim2 multi-channel memory controller # A wrapper for DRAMSim2 multi-channel memory controller
class DRAMSim2(AbstractMemory): class DRAMSim2(AbstractMemory):
type = "DRAMSim2" type = "DRAMSim2"

1
src/mem/DRAMsim3.py
View File

@@ -38,6 +38,7 @@ from m5.citations import add_citation
from m5.params import * from m5.params import *
from m5.objects.AbstractMemory import * from m5.objects.AbstractMemory import *
# A wrapper for DRAMSim3 multi-channel memory controller # A wrapper for DRAMSim3 multi-channel memory controller
class DRAMsim3(AbstractMemory): class DRAMsim3(AbstractMemory):
type = "DRAMsim3" type = "DRAMsim3"

1
src/mem/MemCtrl.py
View File

@@ -43,6 +43,7 @@ from m5.proxy import *
from m5.objects.QoSMemCtrl import * from m5.objects.QoSMemCtrl import *
from m5.citations import add_citation from m5.citations import add_citation
# Enum for memory scheduling algorithms, currently First-Come # Enum for memory scheduling algorithms, currently First-Come
# First-Served and a First-Row Hit then First-Come First-Served # First-Served and a First-Row Hit then First-Come First-Served
class MemSched(Enum): class MemSched(Enum):

1
src/mem/MemInterface.py
View File

@@ -43,6 +43,7 @@ from m5.proxy import *
from m5.objects.AbstractMemory import AbstractMemory from m5.objects.AbstractMemory import AbstractMemory
# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
# channel, rank, bank, row and column, respectively, and going from # channel, rank, bank, row and column, respectively, and going from
# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are # MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are

1
src/mem/NVMInterface.py
View File

@@ -39,6 +39,7 @@ from m5.objects.MemCtrl import MemCtrl
from m5.objects.MemInterface import MemInterface from m5.objects.MemInterface import MemInterface
from m5.objects.DRAMInterface import AddrMap from m5.objects.DRAMInterface import AddrMap
# The following interface aims to model byte-addressable NVM # The following interface aims to model byte-addressable NVM
# The most important system-level performance effects of a NVM # The most important system-level performance effects of a NVM
# are modeled without getting into too much detail of the media itself. # are modeled without getting into too much detail of the media itself.

1
src/mem/cache/Cache.py vendored
View File

@@ -46,6 +46,7 @@ from m5.objects.Prefetcher import BasePrefetcher
from m5.objects.ReplacementPolicies import * from m5.objects.ReplacementPolicies import *
from m5.objects.Tags import * from m5.objects.Tags import *
# Enum for cache clusivity, currently mostly inclusive or mostly # Enum for cache clusivity, currently mostly inclusive or mostly
# exclusive. # exclusive.
class Clusivity(Enum): class Clusivity(Enum):

1
src/mem/qos/QoSMemCtrl.py
View File

@@ -38,6 +38,7 @@ from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject from m5.objects.ClockedObject import ClockedObject
from m5.objects.QoSTurnaround import * from m5.objects.QoSTurnaround import *
# QoS Queue Selection policy used to select packets among same-QoS queues # QoS Queue Selection policy used to select packets among same-QoS queues
class QoSQPolicy(Enum): class QoSQPolicy(Enum):
vals = ["fifo", "lifo", "lrg"] vals = ["fifo", "lifo", "lrg"]

1
src/mem/qos/QoSPolicy.py
View File

@@ -36,6 +36,7 @@
from m5.SimObject import * from m5.SimObject import *
from m5.params import * from m5.params import *
# QoS scheduler policy used to serve incoming transaction # QoS scheduler policy used to serve incoming transaction
class QoSPolicy(SimObject): class QoSPolicy(SimObject):
type = "QoSPolicy" type = "QoSPolicy"

1
src/mem/qos/QoSTurnaround.py
View File

@@ -35,6 +35,7 @@
from m5.SimObject import SimObject from m5.SimObject import SimObject
# QoS Turnaround policy used to select bus state - READ or WRITE # QoS Turnaround policy used to select bus state - READ or WRITE
class QoSTurnaroundPolicy(SimObject): class QoSTurnaroundPolicy(SimObject):
type = "QoSTurnaroundPolicy" type = "QoSTurnaroundPolicy"

1
src/mem/ruby/network/MessageBuffer.py
View File

@@ -40,6 +40,7 @@ from m5.params import *
from m5.proxy import * from m5.proxy import *
from m5.SimObject import SimObject from m5.SimObject import SimObject
# A MessageBuffer inserts random delays to enqueued messages when the # A MessageBuffer inserts random delays to enqueued messages when the
# randomization param is set to 'enabled' or when globally enabled for the # randomization param is set to 'enabled' or when globally enabled for the
# RubySystem and the param is set to 'ruby_system' (default). 'disabled' # RubySystem and the param is set to 'ruby_system' (default). 'disabled'

2
src/mem/slicc/ast/FuncCallExprAST.py
View File

@@ -282,7 +282,7 @@ if (!(${{cvec[0]}})) {
params = "" params = ""
first_param = True first_param = True
for (param_code, type) in zip(cvec, type_vec): for param_code, type in zip(cvec, type_vec):
if first_param: if first_param:
params = str(param_code) params = str(param_code)
first_param = False first_param = False

1
src/mem/slicc/ast/MethodCallExprAST.py
View File

@@ -189,7 +189,6 @@ class ClassMethodCallExprAST(MethodCallExprAST):
return f"[MethodCallExpr: {self.proc_name!r} {self.expr_ast_vec!r}]" return f"[MethodCallExpr: {self.proc_name!r} {self.expr_ast_vec!r}]"
def generate_prefix(self, paramTypes): def generate_prefix(self, paramTypes):
# class method call # class method call
prefix = f"({self.type_ast}::" prefix = f"({self.type_ast}::"
obj_type = self.type_ast.type obj_type = self.type_ast.type

5
src/python/gem5/components/boards/arm_board.py
View File

@@ -88,7 +88,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(), platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(),
release: ArmRelease = ArmDefaultRelease(), release: ArmRelease = ArmDefaultRelease(),
) -> None: ) -> None:
# The platform and the clk has to be set before calling the super class # The platform and the clk has to be set before calling the super class
self._platform = platform self._platform = platform
self._clk_freq = clk_freq self._clk_freq = clk_freq
@@ -117,7 +116,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(AbstractBoard) @overrides(AbstractBoard)
def _setup_board(self) -> None: def _setup_board(self) -> None:
# This board is expected to run full-system simulation. # This board is expected to run full-system simulation.
# Loading ArmFsLinux() from `src/arch/arm/ArmFsWorkload.py` # Loading ArmFsLinux() from `src/arch/arm/ArmFsWorkload.py`
self.workload = ArmFsLinux() self.workload = ArmFsLinux()
@@ -213,7 +211,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
# created. The IO device has to be attached first. This is done in the # created. The IO device has to be attached first. This is done in the
# realview class. # realview class.
if self.get_cache_hierarchy().is_ruby(): if self.get_cache_hierarchy().is_ruby():
# All the on-chip devices are attached in this method. # All the on-chip devices are attached in this method.
self.realview.attachOnChipIO( self.realview.attachOnChipIO(
self.iobus, self.iobus,
@@ -359,7 +356,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(KernelDiskWorkload) @overrides(KernelDiskWorkload)
def _add_disk_to_board(self, disk_image: AbstractResource): def _add_disk_to_board(self, disk_image: AbstractResource):
self._image = CowDiskImage( self._image = CowDiskImage(
child=RawDiskImage( child=RawDiskImage(
read_only=True, image_file=disk_image.get_local_path() read_only=True, image_file=disk_image.get_local_path()
@@ -379,7 +375,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(KernelDiskWorkload) @overrides(KernelDiskWorkload)
def get_default_kernel_args(self) -> List[str]: def get_default_kernel_args(self) -> List[str]:
# The default kernel string is taken from the devices.py file. # The default kernel string is taken from the devices.py file.
return [ return [
"console=ttyAMA0", "console=ttyAMA0",

2
src/python/gem5/components/boards/experimental/lupv_board.py
View File

@@ -90,7 +90,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
memory: AbstractMemorySystem, memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy, cache_hierarchy: AbstractCacheHierarchy,
) -> None: ) -> None:
if cache_hierarchy.is_ruby(): if cache_hierarchy.is_ruby():
raise EnvironmentError("RiscvBoard is not compatible with Ruby") raise EnvironmentError("RiscvBoard is not compatible with Ruby")
@@ -105,7 +104,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
@overrides(AbstractSystemBoard) @overrides(AbstractSystemBoard)
def _setup_board(self) -> None: def _setup_board(self) -> None:
self.workload = RiscvLinux() self.workload = RiscvLinux()
# Initialize all the devices that we want to use on this board # Initialize all the devices that we want to use on this board

1
src/python/gem5/components/boards/x86_board.py
View File

@@ -202,7 +202,6 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
base_entries.append(pci_dev4_inta) base_entries.append(pci_dev4_inta)
def assignISAInt(irq, apicPin): def assignISAInt(irq, apicPin):
assign_8259_to_apic = X86IntelMPIOIntAssignment( assign_8259_to_apic = X86IntelMPIOIntAssignment(
interrupt_type="ExtInt", interrupt_type="ExtInt",
polarity="ConformPolarity", polarity="ConformPolarity",

1
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
View File

@@ -75,7 +75,6 @@ class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy):
@overrides(AbstractCacheHierarchy) @overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None: def incorporate_cache(self, board: AbstractBoard) -> None:
requires(coherence_protocol_required=CoherenceProtocol.CHI) requires(coherence_protocol_required=CoherenceProtocol.CHI)
self.ruby_system = RubySystem() self.ruby_system = RubySystem()

2
src/python/gem5/components/cachehierarchies/classic/no_cache.py
View File

@@ -97,12 +97,10 @@ class NoCache(AbstractClassicCacheHierarchy):
@overrides(AbstractCacheHierarchy) @overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None: def incorporate_cache(self, board: AbstractBoard) -> None:
if board.has_coherent_io(): if board.has_coherent_io():
self._setup_coherent_io_bridge(board) self._setup_coherent_io_bridge(board)
for core in board.get_processor().get_cores(): for core in board.get_processor().get_cores():
core.connect_icache(self.membus.cpu_side_ports) core.connect_icache(self.membus.cpu_side_ports)
core.connect_dcache(self.membus.cpu_side_ports) core.connect_dcache(self.membus.cpu_side_ports)
core.connect_walker_ports( core.connect_walker_ports(

2
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
View File

@@ -86,7 +86,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
@overrides(AbstractCacheHierarchy) @overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None: def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator. # Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports) board.connect_system_port(self.membus.cpu_side_ports)
@@ -117,7 +116,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
self._setup_io_cache(board) self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()): for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side) cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side) cpu.connect_dcache(self.l1dcaches[i].cpu_side)

2
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
View File

@@ -111,7 +111,6 @@ class PrivateL1PrivateL2CacheHierarchy(
@overrides(AbstractCacheHierarchy) @overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None: def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator. # Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports) board.connect_system_port(self.membus.cpu_side_ports)
@@ -148,7 +147,6 @@ class PrivateL1PrivateL2CacheHierarchy(
self._setup_io_cache(board) self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()): for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side) cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side) cpu.connect_dcache(self.l1dcaches[i].cpu_side)

2
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
View File

@@ -107,7 +107,6 @@ class PrivateL1SharedL2CacheHierarchy(
@overrides(AbstractCacheHierarchy) @overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None: def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator. # Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports) board.connect_system_port(self.membus.cpu_side_ports)
@@ -143,7 +142,6 @@ class PrivateL1SharedL2CacheHierarchy(
self._setup_io_cache(board) self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()): for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side) cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side) cpu.connect_dcache(self.l1dcaches[i].cpu_side)

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
View File

@@ -30,7 +30,6 @@ from m5.objects import Directory_Controller
class AbstractDirectory(Directory_Controller): class AbstractDirectory(Directory_Controller):
_version = 0 _version = 0
@classmethod @classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
View File

@@ -30,7 +30,6 @@ from m5.objects import DMA_Controller
class AbstractDMAController(DMA_Controller): class AbstractDMAController(DMA_Controller):
_version = 0 _version = 0
@classmethod @classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
View File

@@ -35,7 +35,6 @@ import math
class AbstractL1Cache(L1Cache_Controller): class AbstractL1Cache(L1Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
View File

@@ -30,7 +30,6 @@ from m5.objects import L2Cache_Controller
class AbstractL2Cache(L2Cache_Controller): class AbstractL2Cache(L2Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py
View File

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
class Directory(AbstractDirectory): class Directory(AbstractDirectory):
def __init__(self, network, cache_line_size, mem_range, port): def __init__(self, network, cache_line_size, mem_range, port):
super().__init__(network, cache_line_size) super().__init__(network, cache_line_size)
self.addr_ranges = [mem_range] self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory() self.directory = RubyDirectoryMemory()

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
View File

@@ -39,10 +39,10 @@ from m5.objects import (
import math import math
# L0Cache_Controller is the ruby backend's terminology corresponding to # L0Cache_Controller is the ruby backend's terminology corresponding to
# L1 cache in stdlib terms. # L1 cache in stdlib terms.
class L1Cache(L0Cache_Controller): class L1Cache(L0Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
View File

@@ -38,10 +38,10 @@ from m5.objects import (
import math import math
# L1Cache_Controller is ruby backend's terminology corresponding to # L1Cache_Controller is ruby backend's terminology corresponding to
# L2Cache in stdlib's terms # L2Cache in stdlib's terms
class L2Cache(L1Cache_Controller): class L2Cache(L1Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
View File

@@ -28,10 +28,10 @@ from m5.objects import MessageBuffer, RubyCache, L2Cache_Controller
import math import math
# L2Cache_Controller is ruby backend's terminology corresponding to # L2Cache_Controller is ruby backend's terminology corresponding to
# L3 cache in stdlib. # L3 cache in stdlib.
class L3Cache(L2Cache_Controller): class L3Cache(L2Cache_Controller):
_version = 0 _version = 0
@classmethod @classmethod

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