misc: Run pre-commit run --all-files

This is reflect the updates made to black when running `pre-commit
autoupdate`.

Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919

src/arch/arm/ArmISA.py

@@ -41,6 +41,7 @@ from m5.objects.ArmPMU import ArmPMU
 from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease
 from m5.objects.BaseISA import BaseISA
 
+
 # Enum for DecoderFlavor
 class DecoderFlavor(Enum):
     vals = ["Generic"]

src/arch/arm/ArmMMU.py

@@ -42,6 +42,7 @@ from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
+
 # Basic stage 1 translation objects
 class ArmTableWalker(ClockedObject):
     type = "ArmTableWalker"

src/arch/isa_parser/isa_parser.py

@@ -374,6 +374,7 @@ def substBitOps(code):
 #
 #####################################################################
 
+
 # Force the argument to be a list.  Useful for flags, where a caller
 # can specify a singleton flag or a list of flags.  Also usful for
 # converting tuples to lists so they can be modified.

src/arch/isa_parser/operand_types.py

@@ -50,7 +50,6 @@ class OperandDesc(object):
     def __init__(
         self, base_cls, dflt_ext, reg_spec, flags=None, sort_pri=None
     ):
-
         from .isa_parser import makeList
 
         # Canonical flag structure is a triple of lists, where each list

src/arch/isa_parser/util.py

@@ -42,6 +42,7 @@ import re
 ###################
 # Utility functions
 
+
 #
 # Indent every line in string 's' by two spaces
 # (except preprocessor directives).

src/arch/micro_asm.py

@@ -187,6 +187,7 @@ def handle_statement(parser, container, statement):
 #
 ##########################################################################
 
+
 # Error handler.  Just call exit.  Output formatted to work under
 # Emacs compile-mode.  Optional 'print_traceback' arg, if set to True,
 # prints a Python stack backtrace too (can be handy when trying to
@@ -231,6 +232,7 @@ reserved_map = {}
 for r in reserved:
     reserved_map[r.lower()] = r
 
+
 # Ignore comments
 def t_ANY_COMMENT(t):
     r"\#[^\n]*(?=\n)"
@@ -360,6 +362,7 @@ def t_ANY_error(t):
 #
 ##########################################################################
 
+
 # Start symbol for a file which may have more than one macroop or rom
 # specification.
 def p_file(t):

src/arch/x86/bios/ACPI.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.SimObject import SimObject
 
+
 # ACPI description table header. Subclasses contain and handle the actual
 # contents as appropriate for that type of table.
 class X86ACPISysDescTable(SimObject):

src/base/Graphics.py

@@ -36,6 +36,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
+
 # Image Formats:
 # Auto option will let gem5 to choose the image format it prefers.
 class ImageFormat(Enum):

src/cpu/testers/traffic_gen/BaseTrafficGen.py

@@ -37,6 +37,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 
+
 # Types of Stream Generators.
 # Those are orthogonal to the other generators in the TrafficGen
 # and are meant to initialize the stream and substream IDs for

src/cpu/testers/traffic_gen/TrafficGen.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.objects.BaseTrafficGen import *
 
+
 # The behaviour of this traffic generator is specified in a
 # configuration file, and this file describes a state transition graph
 # where each state is a specific generator behaviour. Examples include

src/dev/IntPin.py

@@ -29,6 +29,7 @@ INT_SOURCE_ROLE = "Int Source Pin"
 INT_SINK_ROLE = "Int Sink Pin"
 Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
 
+
 # A source pin generally represents a single pin which might connect to
 # multiple sinks.
 class IntSourcePin(VectorPort):

src/dev/ResetPort.py

@@ -29,6 +29,7 @@ RESET_REQUEST_ROLE = "Reset Request"
 RESET_RESPONSE_ROLE = "Reset Response"
 Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE)
 
+
 # ResetRequestPort is an artifact request port for reset purpose.
 class ResetRequestPort(Port):
     def __init__(self, desc):

src/dev/amdgpu/AMDGPU.py

@@ -34,6 +34,7 @@ from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
 from m5.objects.Device import DmaDevice, DmaVirtDevice
 from m5.objects.ClockedObject import ClockedObject
 
+
 # PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
 # correspond to a Vega Frontier Edition hardware device. None of the PCI
 # related values in this class should be changed.

src/dev/arm/FlashDevice.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 
 from m5.objects.AbstractNVM import *
 
+
 # Distribution of the data.
 # sequential: sequential (address n+1 is likely to be on the same plane as n)
 # Random: @TODO Not yet implemented

src/dev/lupio/LupioBLK.py

@@ -31,7 +31,6 @@ from m5.proxy import Parent
 
 
 class LupioBLK(DmaDevice):
-
     type = "LupioBLK"
     cxx_class = "gem5::LupioBLK"
     cxx_header = "dev/lupio/lupio_blk.hh"

src/dev/lupio/LupioPIC.py

@@ -29,7 +29,6 @@ from m5.params import Param
 
 
 class LupioPIC(BasicPioDevice):
-
     type = "LupioPIC"
     cxx_class = "gem5::LupioPIC"
     cxx_header = "dev/lupio/lupio_pic.hh"

src/dev/lupio/LupioRNG.py

@@ -30,7 +30,6 @@ from m5.proxy import Parent
 
 
 class LupioRNG(BasicPioDevice):
-
     type = "LupioRNG"
     cxx_class = "gem5::LupioRNG"
     cxx_header = "dev/lupio/lupio_rng.hh"

src/dev/pci/PciHost.py

@@ -76,7 +76,6 @@ class GenericPciHost(PciHost):
         relocatable=0,
         addr=0,
     ):
-
         busf = bus & 0xFF
         devicef = device & 0x1F
         functionf = function & 0x7

src/dev/sparc/T1000.py

@@ -151,6 +151,7 @@ class T1000(Platform):
     puart0 = Uart8250(pio_addr=0x1F10000000)
 
     iob = Iob()
+
     # Attach I/O devices that are on chip
     def attachOnChipIO(self, bus):
         self.iob.pio = bus.mem_side_ports

src/mem/AddrMapper.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.SimObject import SimObject
 
+
 # An address mapper changes the packet addresses in going from the
 # response port side of the mapper to the request port side. When the
 # response port is queried for the address ranges, it also performs the

src/mem/CommMonitor.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 from m5.objects.System import System
 from m5.SimObject import SimObject
 
+
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
 class CommMonitor(SimObject):

src/mem/DRAMSim2.py

@@ -38,6 +38,7 @@ from citations import add_citation
 from m5.params import *
 from m5.objects.AbstractMemory import *
 
+
 # A wrapper for DRAMSim2 multi-channel memory controller
 class DRAMSim2(AbstractMemory):
     type = "DRAMSim2"

src/mem/DRAMsim3.py

@@ -38,6 +38,7 @@ from m5.citations import add_citation
 from m5.params import *
 from m5.objects.AbstractMemory import *
 
+
 # A wrapper for DRAMSim3 multi-channel memory controller
 class DRAMsim3(AbstractMemory):
     type = "DRAMsim3"

src/mem/MemCtrl.py

@@ -43,6 +43,7 @@ from m5.proxy import *
 from m5.objects.QoSMemCtrl import *
 from m5.citations import add_citation
 
+
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
 class MemSched(Enum):

src/mem/MemInterface.py

@@ -43,6 +43,7 @@ from m5.proxy import *
 
 from m5.objects.AbstractMemory import AbstractMemory
 
+
 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
 # channel, rank, bank, row and column, respectively, and going from
 # MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are

src/mem/NVMInterface.py

@@ -39,6 +39,7 @@ from m5.objects.MemCtrl import MemCtrl
 from m5.objects.MemInterface import MemInterface
 from m5.objects.DRAMInterface import AddrMap
 
+
 # The following interface aims to model byte-addressable NVM
 # The most important system-level performance effects of a NVM
 # are modeled without getting into too much detail of the media itself.

src/mem/cache/Cache.py

@@ -46,6 +46,7 @@ from m5.objects.Prefetcher import BasePrefetcher
 from m5.objects.ReplacementPolicies import *
 from m5.objects.Tags import *
 
+
 # Enum for cache clusivity, currently mostly inclusive or mostly
 # exclusive.
 class Clusivity(Enum):

src/mem/qos/QoSMemCtrl.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.QoSTurnaround import *
 
+
 # QoS Queue Selection policy used to select packets among same-QoS queues
 class QoSQPolicy(Enum):
     vals = ["fifo", "lifo", "lrg"]

src/mem/qos/QoSPolicy.py

@@ -36,6 +36,7 @@
 from m5.SimObject import *
 from m5.params import *
 
+
 # QoS scheduler policy used to serve incoming transaction
 class QoSPolicy(SimObject):
     type = "QoSPolicy"

src/mem/qos/QoSTurnaround.py

@@ -35,6 +35,7 @@
 
 from m5.SimObject import SimObject
 
+
 # QoS Turnaround policy used to select bus state - READ or WRITE
 class QoSTurnaroundPolicy(SimObject):
     type = "QoSTurnaroundPolicy"

src/mem/ruby/network/MessageBuffer.py

@@ -40,6 +40,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
+
 # A MessageBuffer inserts random delays to enqueued messages when the
 # randomization param is set to 'enabled' or when globally enabled for the
 # RubySystem and the param is set to 'ruby_system' (default). 'disabled'

src/mem/slicc/ast/FuncCallExprAST.py

@@ -282,7 +282,7 @@ if (!(${{cvec[0]}})) {
             params = ""
             first_param = True
 
-            for (param_code, type) in zip(cvec, type_vec):
+            for param_code, type in zip(cvec, type_vec):
                 if first_param:
                     params = str(param_code)
                     first_param = False

src/mem/slicc/ast/MethodCallExprAST.py

@@ -189,7 +189,6 @@ class ClassMethodCallExprAST(MethodCallExprAST):
         return f"[MethodCallExpr: {self.proc_name!r} {self.expr_ast_vec!r}]"
 
     def generate_prefix(self, paramTypes):
-
         # class method call
         prefix = f"({self.type_ast}::"
         obj_type = self.type_ast.type

src/python/gem5/components/boards/arm_board.py

@@ -88,7 +88,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
         platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(),
         release: ArmRelease = ArmDefaultRelease(),
     ) -> None:
-
         # The platform and the clk has to be set before calling the super class
         self._platform = platform
         self._clk_freq = clk_freq
@@ -117,7 +116,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(AbstractBoard)
     def _setup_board(self) -> None:
-
         # This board is expected to run full-system simulation.
         # Loading ArmFsLinux() from `src/arch/arm/ArmFsWorkload.py`
         self.workload = ArmFsLinux()
@@ -213,7 +211,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
         # created. The IO device has to be attached first. This is done in the
         # realview class.
         if self.get_cache_hierarchy().is_ruby():
-
             # All the on-chip devices are attached in this method.
             self.realview.attachOnChipIO(
                 self.iobus,
@@ -359,7 +356,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(KernelDiskWorkload)
     def _add_disk_to_board(self, disk_image: AbstractResource):
-
         self._image = CowDiskImage(
             child=RawDiskImage(
                 read_only=True, image_file=disk_image.get_local_path()
@@ -379,7 +375,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(KernelDiskWorkload)
     def get_default_kernel_args(self) -> List[str]:
-
         # The default kernel string is taken from the devices.py file.
         return [
             "console=ttyAMA0",

src/python/gem5/components/boards/experimental/lupv_board.py

@@ -90,7 +90,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
         memory: AbstractMemorySystem,
         cache_hierarchy: AbstractCacheHierarchy,
     ) -> None:
-
         if cache_hierarchy.is_ruby():
             raise EnvironmentError("RiscvBoard is not compatible with Ruby")
 
@@ -105,7 +104,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
 
     @overrides(AbstractSystemBoard)
     def _setup_board(self) -> None:
-
         self.workload = RiscvLinux()
 
         # Initialize all the devices that we want to use on this board

src/python/gem5/components/boards/x86_board.py

@@ -202,7 +202,6 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
         base_entries.append(pci_dev4_inta)
 
         def assignISAInt(irq, apicPin):
-
             assign_8259_to_apic = X86IntelMPIOIntAssignment(
                 interrupt_type="ExtInt",
                 polarity="ConformPolarity",

src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

@@ -75,7 +75,6 @@ class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(coherence_protocol_required=CoherenceProtocol.CHI)
 
         self.ruby_system = RubySystem()

src/python/gem5/components/cachehierarchies/classic/no_cache.py

@@ -97,12 +97,10 @@ class NoCache(AbstractClassicCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         if board.has_coherent_io():
             self._setup_coherent_io_bridge(board)
 
         for core in board.get_processor().get_cores():
-
             core.connect_icache(self.membus.cpu_side_ports)
             core.connect_dcache(self.membus.cpu_side_ports)
             core.connect_walker_ports(

src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py

@@ -86,7 +86,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -117,7 +116,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -111,7 +111,6 @@ class PrivateL1PrivateL2CacheHierarchy(
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -148,7 +147,6 @@ class PrivateL1PrivateL2CacheHierarchy(
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

@@ -107,7 +107,6 @@ class PrivateL1SharedL2CacheHierarchy(
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -143,7 +142,6 @@ class PrivateL1SharedL2CacheHierarchy(
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

@@ -30,7 +30,6 @@ from m5.objects import Directory_Controller
 
 
 class AbstractDirectory(Directory_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py

@@ -30,7 +30,6 @@ from m5.objects import DMA_Controller
 
 
 class AbstractDMAController(DMA_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py

@@ -35,7 +35,6 @@ import math
 
 
 class AbstractL1Cache(L1Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py

@@ -30,7 +30,6 @@ from m5.objects import L2Cache_Controller
 
 
 class AbstractL2Cache(L2Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
 
 class Directory(AbstractDirectory):
     def __init__(self, network, cache_line_size, mem_range, port):
-
         super().__init__(network, cache_line_size)
         self.addr_ranges = [mem_range]
         self.directory = RubyDirectoryMemory()

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -39,10 +39,10 @@ from m5.objects import (
 
 import math
 
+
 # L0Cache_Controller is the ruby backend's terminology corresponding to
 # L1 cache in stdlib terms.
 class L1Cache(L0Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -38,10 +38,10 @@ from m5.objects import (
 
 import math
 
+
 # L1Cache_Controller is ruby backend's terminology corresponding to
 # L2Cache in stdlib's terms
 class L2Cache(L1Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

@@ -28,10 +28,10 @@ from m5.objects import MessageBuffer, RubyCache, L2Cache_Controller
 
 import math
 
+
 # L2Cache_Controller is ruby backend's terminology corresponding to
 # L3 cache in stdlib.
 class L3Cache(L2Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
 
 class Directory(AbstractDirectory):
     def __init__(self, network, cache_line_size, mem_range, port):
-
         super().__init__(network, cache_line_size)
         self.addr_ranges = [mem_range]
         self.directory = RubyDirectoryMemory()

src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py

@@ -37,7 +37,6 @@ class Directory(AbstractDirectory):
     """
 
     def __init__(self, network, cache_line_size, mem_range, port):
-
         super().__init__(network, cache_line_size)
         self.addr_ranges = [mem_range]
         self.directory = RubyDirectoryMemory()

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py

@@ -45,6 +45,7 @@ from .core_complex import CoreComplex
 from .octopi_network import OctopiNetwork
 from .ruby_network_components import RubyRouter, RubyExtLink, RubyIntLink
 
+
 # CoreComplex sub-systems own the L1, L2, L3 controllers
 # OctopiCache owns the directory controllers
 # RubySystem owns the DMA Controllers
@@ -85,7 +86,6 @@ class OctopiCache(
         self._is_fullsystem = is_fullsystem
 
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(
             coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL
         )

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py

@@ -32,6 +32,7 @@ from .ruby_network_components import (
     RubyIntLink,
 )
 
+
 # . The Network owns all routers, all int links and all ext links that are not in CCD's.
 # . The CCD subsystems are not of type RubyNetwork, so we need to copy the references of
 # routers and links to OctopiNetwork._routers, ._int_links, and ._ext_links; which will

src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py

@@ -80,7 +80,6 @@ class MESIThreeLevelCacheHierarchy(
         self._num_l3_banks = num_l3_banks
 
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(
             coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL
         )

src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -76,7 +76,6 @@ class MESITwoLevelCacheHierarchy(
         self._num_l2_banks = num_l2_banks
 
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL)
 
         cache_line_size = board.get_cache_line_size()

src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -58,7 +58,6 @@ class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(coherence_protocol_required=CoherenceProtocol.MI_EXAMPLE)
 
         self.ruby_system = RubySystem()

src/python/gem5/components/memory/dram_interfaces/hbm.py

@@ -201,7 +201,6 @@ class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
 # on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity
 # of 4GiB.
 class HBM_2000_4H_1x64(DRAMInterface):
-
     # 64-bit interface for a single pseudo channel
     device_bus_width = 64
 

src/python/gem5/components/memory/hbm.py

@@ -137,7 +137,6 @@ class HighBandwidthMemory(ChanneledMemory):
 
     @overrides(ChanneledMemory)
     def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
-
         intlv_bits = log(self._num_channels, 2)
         mask_list = []
 

src/python/gem5/components/processors/base_cpu_core.py

@@ -93,7 +93,6 @@ class BaseCPUCore(AbstractCore):
 
     @overrides(AbstractCore)
     def is_kvm_core(self) -> bool:
-
         try:
             from m5.objects import BaseKvmCPU
 
@@ -118,7 +117,6 @@ class BaseCPUCore(AbstractCore):
     @overrides(AbstractCore)
     def connect_walker_ports(self, port1: Port, port2: Port) -> None:
         if self.get_isa() == ISA.ARM:
-
             # Unlike X86 and RISCV MMU, the ARM MMU has two L1 TLB walker ports
             # named `walker` and `stage2_walker` for both data and instruction.
             # The gem5 standard library currently supports one TLB walker port
@@ -144,7 +142,6 @@ class BaseCPUCore(AbstractCore):
         interrupt_requestor: Optional[Port] = None,
         interrupt_responce: Optional[Port] = None,
     ) -> None:
-
         # TODO: This model assumes that we will only create an interrupt
         # controller as we require it. Not sure how true this is in all cases.
         self.core.createInterruptController()

src/python/gem5/components/processors/base_cpu_processor.py

@@ -71,7 +71,6 @@ class BaseCPUProcessor(AbstractProcessor):
 
     @overrides(AbstractProcessor)
     def incorporate_processor(self, board: AbstractBoard) -> None:
-
         if any(core.is_kvm_core() for core in self.get_cores()):
             board.kvm_vm = self.kvm_vm
             # To get the KVM CPUs to run on different host CPUs

src/python/gem5/components/processors/simple_core.py

@@ -44,7 +44,6 @@ class SimpleCore(BaseCPUCore):
     def __init__(
         self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
     ):
-
         # If the ISA is not specified, we infer it via the `get_runtime_isa`
         # function.
         if isa:

src/python/gem5/components/processors/switchable_processor.py

@@ -52,7 +52,6 @@ class SwitchableProcessor(AbstractProcessor):
         switchable_cores: Dict[str, List[SimpleCore]],
         starting_cores: str,
     ) -> None:
-
         if starting_cores not in switchable_cores.keys():
             raise AssertionError(
                 f"Key {starting_cores} cannot be found in the "
@@ -85,7 +84,6 @@ class SwitchableProcessor(AbstractProcessor):
 
     @overrides(AbstractProcessor)
     def incorporate_processor(self, board: AbstractBoard) -> None:
-
         # This is a bit of a hack. The `m5.switchCpus` function, used in the
         # "switch_to_processor" function, requires the System simobject as an
         # argument. We therefore need to store the board when incorporating the
@@ -119,7 +117,6 @@ class SwitchableProcessor(AbstractProcessor):
                 yield core
 
     def switch_to_processor(self, switchable_core_key: str):
-
         # Run various checks.
         if not hasattr(self, "_board"):
             raise AssertionError("The processor has not been incorporated.")

src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py

@@ -97,7 +97,6 @@ class RISCVMatchedCacheHierarchy(
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -135,7 +134,6 @@ class RISCVMatchedCacheHierarchy(
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/resources/client_api/client_wrapper.py

@@ -63,7 +63,6 @@ class ClientWrapper:
         clients: Optional[List[str]] = None,
         gem5_version: Optional[str] = core.gem5Version,
     ) -> Dict[str, List[str]]:
-
         clients_to_search = (
             list(self.clients.keys()) if clients is None else clients
         )

src/python/gem5/resources/downloader.py

@@ -369,7 +369,6 @@ def get_resource(
             with tarfile.open(download_dest) as f:
 
                 def is_within_directory(directory, target):
-
                     abs_directory = os.path.abspath(directory)
                     abs_target = os.path.abspath(target)
 
@@ -380,7 +379,6 @@ def get_resource(
                 def safe_extract(
                     tar, path=".", members=None, *, numeric_owner=False
                 ):
-
                     for member in tar.getmembers():
                         member_path = os.path.join(path, member.name)
                         if not is_within_directory(path, member_path):

src/python/gem5/resources/looppoint.py

@@ -491,7 +491,6 @@ class LooppointJsonLoader(Looppoint):
         with open(_path) as file:
             json_contents = json.load(file)
             for rid in json_contents:
-
                 start_pc = int(json_contents[rid]["simulation"]["start"]["pc"])
                 start_globl = int(
                     json_contents[rid]["simulation"]["start"]["global"]

src/python/gem5/resources/resource.py

@@ -863,7 +863,6 @@ def obtain_resource(
 
     # If the "url" field is specified, the resoruce must be downloaded.
     if "url" in resource_json and resource_json["url"]:
-
         # If the `to_path` parameter is set, we use that as the path to which
         # the resource is to be downloaded. Otherwise, default to the
         # `resource_directory` parameter plus the resource ID.

src/python/gem5/simulate/simulator.py

@@ -464,7 +464,7 @@ class Simulator:
         """
         start = 0
         to_return = []
-        for (exit_event, tick) in self._tick_stopwatch:
+        for exit_event, tick in self._tick_stopwatch:
             if exit_event == ExitEvent.WORKBEGIN:
                 start = tick
             elif exit_event == ExitEvent.WORKEND:
@@ -480,7 +480,6 @@ class Simulator:
         """
 
         if not self._instantiated:
-
             # Before anything else we run the AbstractBoard's
             # `_pre_instantiate` function.
             self._board._pre_instantiate()
@@ -557,7 +556,6 @@ class Simulator:
 
         # This while loop will continue until an a generator yields True.
         while True:
-
             self._last_exit_event = m5.simulate(max_ticks)
 
             # Translate the exit event cause to the exit event enum.
@@ -584,7 +582,7 @@ class Simulator:
                 # If the user has specified their own generator for this exit
                 # event, use it.
                 exit_on_completion = next(self._on_exit_event[exit_enum])
-            except (StopIteration):
+            except StopIteration:
                 # If the user's generator has ended, throw a warning and use
                 # the default generator for this exit event.
                 warn(

src/python/gem5/utils/multiprocessing/context.py

@@ -33,6 +33,7 @@ multiprocessing module (i.e., cpython/Lib/multiprocessing/).
 from multiprocessing import context, process
 from multiprocessing.context import DefaultContext
 
+
 # The `_start_method` must be `None` for the `Spawn_gem5Process` class.
 # Otherwise, in `_bootstrap` in the `BaseProcess` it will try to force the
 # `_start_method` to be gem5-specific, which the `multiprocessing` module

src/python/gem5/utils/progress_bar.py

@@ -55,6 +55,7 @@ except ImportError:
     tqdm = FakeTQDM()
     _have_tqdm = False
 
+
 # Hook for the progress bar
 def progress_hook(t):
     if not _have_tqdm:

src/python/m5/SimObject.py

@@ -1252,7 +1252,7 @@ class SimObject(object, metaclass=MetaSimObject):
         # The order of the dict is implementation dependent, so sort
         # it based on the key (name) to ensure the order is the same
         # on all hosts
-        for (name, child) in sorted(self._children.items()):
+        for name, child in sorted(self._children.items()):
             for obj in child.descendants():
                 yield obj
 
@@ -1275,7 +1275,7 @@ class SimObject(object, metaclass=MetaSimObject):
     def connectPorts(self):
         # Sort the ports based on their attribute name to ensure the
         # order is the same on all hosts
-        for (attr, portRef) in sorted(self._port_refs.items()):
+        for attr, portRef in sorted(self._port_refs.items()):
             portRef.ccConnect()
 
     # Default function for generating the device structure.

src/python/m5/params.py

@@ -453,6 +453,7 @@ VectorParam = ParamFactory(VectorParamDesc)
 #
 #####################################################################
 
+
 # String-valued parameter.  Just mixin the ParamValue class with the
 # built-in str class.
 class String(ParamValue, str):
@@ -1524,10 +1525,11 @@ class Time(ParamValue):
 # derive the new type from the appropriate base class on the fly.
 
 allEnums = {}
+
+
 # Metaclass for Enum types
 class MetaEnum(MetaParamValue):
     def __new__(mcls, name, bases, dict):
-
         cls = super().__new__(mcls, name, bases, dict)
         allEnums[name] = cls
         return cls
@@ -1963,6 +1965,7 @@ class MemoryBandwidth(float, ParamValue):
 # "Constants"... handy aliases for various values.
 #
 
+
 # Special class for NULL pointers.  Note the special check in
 # make_param_value() above that lets these be assigned where a
 # SimObject is required.
@@ -2030,6 +2033,7 @@ AllMemory = AddrRange(0, MaxAddr)
 #
 #####################################################################
 
+
 # Port reference: encapsulates a reference to a particular port on a
 # particular SimObject.
 class PortRef(object):
@@ -2371,6 +2375,7 @@ SlavePort = ResponsePort
 VectorMasterPort = VectorRequestPort
 VectorSlavePort = VectorResponsePort
 
+
 # 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
 # proxy objects (via set_param_desc()) so that proxy error messages
 # make sense.

src/python/m5/simulate.py

@@ -65,6 +65,7 @@ _drain_manager = _m5.drain.DrainManager.instance()
 
 _instantiated = False  # Has m5.instantiate() been called?
 
+
 # The final call to instantiate the SimObject graph and initialize the
 # system.
 def instantiate(ckpt_dir=None):

src/python/m5/ticks.py

@@ -29,6 +29,7 @@ import decimal
 import sys
 from m5.util import warn
 
+
 # fix the global frequency
 def fixGlobalFrequency():
     import _m5.core

src/python/m5/util/__init__.py

@@ -48,6 +48,7 @@ from . import convert
 from .attrdict import attrdict, multiattrdict, optiondict
 from .multidict import multidict
 
+
 # panic() should be called when something happens that should never
 # ever happen regardless of what the user does (i.e., an acutal m5
 # bug).

src/python/m5/util/terminal_formatter.py

@@ -45,7 +45,6 @@ class TerminalFormatter:
         return w, h
 
     def __get_paragraphs(self, text, flatten=False):
-
         """
         This function takes a text and returns a list of constituent
         paragraphs, defining a paragraph as a block of text separated from

src/sim/ClockDomain.py

@@ -37,6 +37,7 @@ from m5.params import *
 from m5.SimObject import SimObject
 from m5.proxy import *
 
+
 # Abstract clock domain
 class ClockDomain(SimObject):
     type = "ClockDomain"

src/sim/DVFSHandler.py

@@ -37,6 +37,7 @@ from m5.params import *
 from m5.SimObject import SimObject
 from m5.proxy import *
 
+
 # The handler in its current form is design to be centeralized, one per system
 # and manages all the source clock domains (SrcClockDomain) it is configured to
 # handle.  The specific voltage and frequency points are configured per clock

src/sim/PowerDomain.py

@@ -39,6 +39,7 @@ import sys
 from m5.params import *
 from m5.objects.PowerState import PowerState
 
+
 # A power domain groups multiple ClockedObjects and creates a
 # hierarchy in which follower ClockedObjects (caches for example) can
 # change power state depeding on what the leader objects (CPUs for

src/sim/PowerState.py

@@ -38,6 +38,7 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 
+
 # Enumerate set of allowed power states that can be used by a clocked object.
 # The list is kept generic to express a base minimal set.
 # State definition :-

src/sim/Root.py

@@ -32,7 +32,6 @@ from m5.util import fatal
 
 
 class Root(SimObject):
-
     _the_instance = None
 
     def __new__(cls, **kwargs):

src/sim/SubSystem.py

@@ -36,6 +36,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
+
 # An empty simobject. Used for organizing simobjects
 # into logical groups as subsystems of a larger
 # system. For example, if we wanted to build a cpu cluster

src/sim/power/MathExprPowerModel.py

@@ -37,6 +37,7 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.objects.PowerModelState import PowerModelState
 
+
 # Represents a power model for a simobj
 class MathExprPowerModel(PowerModelState):
     type = "MathExprPowerModel"

src/sim/power/PowerModel.py

@@ -37,6 +37,7 @@ from m5.SimObject import *
 from m5.params import *
 from m5.proxy import Parent
 
+
 # Enum for a type of  power model
 class PMType(Enum):
     vals = ["All", "Static", "Dynamic"]

src/sim/power/PowerModelState.py

@@ -36,6 +36,7 @@
 from m5.SimObject import *
 from m5.params import *
 
+
 # Represents a power model for a simobj
 class PowerModelState(SimObject):
     type = "PowerModelState"

src/sim/power/ThermalDomain.py

@@ -36,6 +36,7 @@
 from m5.SimObject import *
 from m5.params import *
 
+
 # Represents a group of simobj which produce heat
 class ThermalDomain(SimObject):
     type = "ThermalDomain"

src/systemc/core/SystemC.py

@@ -25,6 +25,7 @@
 
 from m5.SimObject import SimObject, cxxMethod
 
+
 # This class represents the systemc kernel. There should be exactly one in the
 # simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats,
 # etc.) and manages the lifecycle of the systemc simulation accordingly.