misc: Run pre-commit run --all-files

This is reflect the updates made to black when running `pre-commit
autoupdate`.

Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919

configs/common/cores/arm/HPI.py

@@ -44,6 +44,7 @@ at: http://www.arm.com/ResearchEnablement/SystemModeling
 
 from m5.objects import *
 
+
 # Simple function to allow a string of [01x_] to be converted into a
 # mask and value for use with MinorFUTiming
 def make_implicant(implicant_string):

configs/common/cores/arm/O3_ARM_Etrace.py

@@ -36,6 +36,7 @@
 from m5.objects import *
 from .O3_ARM_v7a import O3_ARM_v7a_3
 
+
 # O3_ARM_v7a_3 adapted to generate elastic traces
 class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3):
     # Make the number of entries in the ROB, LQ and SQ very

configs/common/cores/arm/O3_ARM_v7a.py

@@ -26,6 +26,7 @@
 
 from m5.objects import *
 
+
 # Simple ALU Instructions have a latency of 1
 class O3_ARM_v7a_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]

configs/common/cores/arm/ex5_LITTLE.py

@@ -31,6 +31,7 @@ from m5.objects import *
 #                ex5 LITTLE core (based on the ARM Cortex-A7)
 # -----------------------------------------------------------------------
 
+
 # Simple ALU Instructions have a latency of 3
 class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
     opList = [OpDesc(opClass="IntAlu", opLat=4)]

configs/common/cores/arm/ex5_big.py

@@ -31,6 +31,7 @@ from m5.objects import *
 #                ex5 big core (based on the ARM Cortex-A15)
 # -----------------------------------------------------------------------
 
+
 # Simple ALU Instructions have a latency of 1
 class ex5_big_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]