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mem,ext: Integrating DRAMSim3 with gem5

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Adding DRAMSim3 source code to the gem5 source code, the original
code was taken from umd-memsys github at https://github.com/umd-memsys/

Change-Id: I32c982206f33b0acf2121f322d15baa064c412c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31757
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Mahyar Samani
2020-07-27 15:26:04 +00:00
parent acd63fe5ac
commit dde093b283
8 changed files with 1069 additions and 0 deletions
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6
src/mem/SConscript
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@@ -91,6 +91,11 @@ if env['HAVE_DRAMSIM']:
Source('dramsim2_wrapper.cc')
Source('dramsim2.cc')
if env['HAVE_DRAMSIM3']:
SimObject('DRAMsim3.py')
Source('dramsim3_wrapper.cc')
Source('dramsim3.cc')
SimObject('MemChecker.py')
Source('mem_checker.cc')
Source('mem_checker_monitor.cc')
@@ -115,6 +120,7 @@ DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
DebugFlag("DRAMsim3")
DebugFlag('HMCController')
DebugFlag('SerialLink')
DebugFlag('TokenPort')