Enable m5ops and change cache line size to 32

src/mem/dramsys_wrapper.cc

@@ -89,24 +89,6 @@ tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_fw(
     // Subtract base address offset
     payload.set_address(payload.get_address() - range.start());
 
-    if (payload.get_address() < 0x4000 && payload.is_write() && phase == tlm::BEGIN_REQ)
-    {
-        char *msg = reinterpret_cast<char*>(payload.get_data_ptr());
-        for (std::size_t i = 0; i < payload.get_data_length(); i++)
-        {
-            if (msg[i] != '\0')
-            {
-                message.push_back(msg[i]);
-            }
-            else
-            {
-                std::cout << message << std::endl;
-                message.clear();
-                break;
-            }
-        }
-    }
-
     return iSocket->nb_transport_fw(payload, phase, fwDelay);
 }
 

src/mem/dramsys_wrapper.hh

@@ -84,7 +84,6 @@ class DRAMSysWrapper : public sc_core::sc_module
     tlm_utils::simple_target_socket<DRAMSysWrapper> tSocket;
 
     std::shared_ptr<::DRAMSys::DRAMSys> dramsys;
-    std::string message;
 
     AddrRange range;
 };