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style: remove trailing whitespace

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Result of running 'hg m5style --skip-all --fix-white -a'.
This commit is contained in:
Steve Reinhardt
2016-02-06 17:21:18 -08:00
parent c8c82f09a2
commit dc8018a5c3
90 changed files with 330 additions and 330 deletions
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24
src/arch/alpha/isa/decoder.isa
View File

@@ -349,7 +349,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 0; i < 8; ++i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
temp += (ra_ub >= rb_ub) ?
temp += (ra_ub >= rb_ub) ?
(ra_ub - rb_ub) : (rb_ub - ra_ub);
hi += 8;
lo += 8;
@@ -378,15 +378,15 @@ decode OPCODE default Unknown::unknown() {
if (!(temp<7:0>)) { temp >>= 8; count += 8; }
if (!(temp<3:0>)) { temp >>= 4; count += 4; }
if (!(temp<1:0>)) { temp >>= 2; count += 2; }
if (!(temp<0:0> & ULL(0x1))) {
temp >>= 1; count += 1;
if (!(temp<0:0> & ULL(0x1))) {
temp >>= 1; count += 1;
}
if (!(temp<0:0> & ULL(0x1))) count += 1;
Rc = count;
}}, IntAluOp);
0x34: unpkbw({{
0x34: unpkbw({{
Rc = (Rb_uq<7:0>
| (Rb_uq<15:8> << 16)
| (Rb_uq<23:16> << 32)
@@ -415,7 +415,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb_uq<hi:lo>;
temp = ((temp << 8)
temp = ((temp << 8)
| ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -431,7 +431,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16)
temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -447,7 +447,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
temp = ((temp << 8)
temp = ((temp << 8)
| ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -463,7 +463,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 3; i >= 0; --i) {
uint16_t ra_sw = Ra_uq<hi:lo>;
uint16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16)
temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -479,7 +479,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb_uq<hi:lo>;
temp = ((temp << 8)
temp = ((temp << 8)
| ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -495,7 +495,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 3; i >= 0; --i) {
uint16_t ra_uw = Ra_uq<hi:lo>;
uint16_t rb_uw = Rb_uq<hi:lo>;
temp = ((temp << 16)
temp = ((temp << 16)
| ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;
@@ -511,7 +511,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb_uq<hi:lo>;
temp = ((temp << 8)
temp = ((temp << 8)
| ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 8;
@@ -527,7 +527,7 @@ decode OPCODE default Unknown::unknown() {
for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16)
temp = ((temp << 16)
| ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
: Rb_uq<hi:lo>));
hi -= 16;

2
src/arch/alpha/linux/linux.hh
View File

@@ -127,7 +127,7 @@ class AlphaLinux : public Linux
static const unsigned TGT_RLIMIT_AS = 7;
static const unsigned TGT_RLIMIT_NOFILE = 6;
static const unsigned TGT_RLIMIT_MEMLOCK = 9;
typedef struct {
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */

8
src/arch/alpha/process.cc
View File

@@ -75,7 +75,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
if(elfObject)
{
// modern glibc uses a bunch of auxiliary vectors to set up
// modern glibc uses a bunch of auxiliary vectors to set up
// TLS as well as do a bunch of other stuff
// these vectors go on the bottom of the stack, below argc/argv/envp
// pointers but above actual arg strings
@@ -111,10 +111,10 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
}
int space_needed =
argv_array_size +
envp_array_size +
argv_array_size +
envp_array_size +
auxv_array_size +
arg_data_size +
arg_data_size +
env_data_size;
if (space_needed < 32*1024)

6
src/arch/alpha/tlb.cc
View File

@@ -230,9 +230,9 @@ TLB::checkCacheability(RequestPtr &req, bool itb)
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
}
// We shouldn't be able to read from an uncachable address in Alpha as
// we don't have a ROM and we don't want to try to fetch from a device
// register as we destroy any data that is clear-on-read.
if (req->isUncacheable() && itb)
// we don't have a ROM and we don't want to try to fetch from a device
// register as we destroy any data that is clear-on-read.
if (req->isUncacheable() && itb)
return std::make_shared<UnimpFault>(
"CPU trying to fetch from uncached I/O");

2
src/arch/arm/SConscript
View File

@@ -45,7 +45,7 @@ Import('*')
if env['TARGET_ISA'] == 'arm':
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308
# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
Source('faults.cc')

2
src/arch/arm/interrupts.cc
View File

@@ -39,7 +39,7 @@
#include "arch/arm/interrupts.hh"
#include "arch/arm/system.hh"
ArmISA::Interrupts *
ArmInterruptsParams::create()
{

2
src/arch/arm/isa/bitfields.isa
View File

@@ -65,7 +65,7 @@ def bitfield OPCODE_18 opcode18;
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
def bitfield OPC2 opc2;
def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_6 opcode6;
def bitfield OPCODE_4 opcode4;

16
src/arch/arm/isa/formats/pred.isa
View File

@@ -41,7 +41,7 @@
// Authors: Stephen Hines
let {{
calcCcCode = '''
if (%(canOverflow)s){
cprintf("canOverflow: %%d\\n", Rd < resTemp);
@@ -52,7 +52,7 @@ let {{
_iz = (resTemp == 0);
_iv = %(ivValue)s;
_ic = %(icValue)s;
CondCodesNZ = (_in << 1) | (_iz);
CondCodesC = _ic;
CondCodesV = _iv;
@@ -79,7 +79,7 @@ let {{
iv = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
canOverflow = "true"
canOverflow = "true"
icReg = icImm = iv = '0'
elif flagtype == "add":
icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
@@ -94,12 +94,12 @@ let {{
icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
iv = 'CondCodesV'
return (calcCcCode % {"icValue" : icReg,
"ivValue" : iv,
return (calcCcCode % {"icValue" : icReg,
"ivValue" : iv,
"negBit" : negBit,
"canOverflow" : canOverflow },
calcCcCode % {"icValue" : icImm,
"ivValue" : iv,
calcCcCode % {"icValue" : icImm,
"ivValue" : iv,
"negBit" : negBit,
"canOverflow" : canOverflow })
@@ -116,7 +116,7 @@ let {{
negBit = 63
elif flagtype == "overflow":
icVaule = ivValue = '0'
canOverflow = "true"
canOverflow = "true"
elif flagtype == "add":
icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'

2
src/arch/arm/linux/linux.hh
View File

@@ -177,7 +177,7 @@ class ArmLinux32 : public Linux
uint32_t freehigh; /* Available high memory size */
uint32_t mem_unit; /* Memory unit size in bytes */
} tgt_sysinfo;
/// For getrusage().
struct rusage {
struct timeval ru_utime; //!< user time used

2
src/arch/arm/stacktrace.cc
View File

@@ -170,7 +170,7 @@ namespace ArmISA
StackTrace::dump()
{
DPRINTFN("------ Stack ------\n");
DPRINTFN(" Not implemented\n");
}
#endif

6
src/arch/mips/isa/decoder.isa
View File

@@ -359,7 +359,7 @@ decode OPCODE_HI default Unknown::unknown() {
Rt &= 0xFFFFE7FF;
}
}});
0x4: mtc0({{
0x4: mtc0({{
CP0_RD_SEL = Rt;
CauseReg cause = Cause;
IntCtlReg intCtl = IntCtl;
@@ -1238,7 +1238,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: CP1Unimpl::unknown();
0x7: CP1Unimpl::unknown();
//Table A-16 MIPS32 COP1 Encoding of Function
//Table A-16 MIPS32 COP1 Encoding of Function
//Field When rs=W
0x4: decode FUNCTION {
format FloatConvertOp {
@@ -1867,7 +1867,7 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x7: precr_sra_r_ph_w({{
Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
SIMD_FMT_W, ROUND);
SIMD_FMT_W, ROUND);
}});
}
}

4
src/arch/mips/linux/linux.hh
View File

@@ -125,7 +125,7 @@ class MipsLinux : public Linux
/// assign themselves to process IDs reserved for
/// the root users.
static const int NUM_ROOT_PROCS = 2;
typedef struct {
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
@@ -140,7 +140,7 @@ class MipsLinux : public Linux
uint32_t freehigh; /* Available high memory size */
uint32_t mem_unit; /* Memory unit size in bytes */
} tgt_sysinfo;
};
#endif

2
src/arch/mips/linux/process.cc
View File

@@ -77,7 +77,7 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
switch (op) {
case 45:
{
{
// GSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(bufPtr);
// I don't think this exactly matches the HW FPCR

2
src/arch/mips/pagetable.hh
View File

@@ -65,7 +65,7 @@ struct PTE
bool V1; // Odd entry Valid Bit
uint8_t C1; // Cache Coherency Bits (3 bits)
/*
/*
* The next few variables are put in as optimizations to reduce
* TLB lookup overheads. For a given Mask, what is the address shift
* amount, and what is the OffsetMask

2
src/arch/power/SConscript
View File

@@ -32,7 +32,7 @@ Import('*')
if env['TARGET_ISA'] == 'power':
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308
# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
Source('insts/branch.cc')

2
src/arch/sparc/interrupts.cc
View File

@@ -29,7 +29,7 @@
*/
#include "arch/sparc/interrupts.hh"
SparcISA::Interrupts *
SparcInterruptsParams::create()
{

8
src/arch/sparc/linux/linux.hh
View File

@@ -78,8 +78,8 @@ class SparcLinux : public Linux
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
static const unsigned TGT_MAP_FIXED = 0x10;
typedef struct {
typedef struct {
int64_t uptime; /* Seconds since boot */
uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
uint64_t totalram; /* Total usable main memory size */
@@ -151,7 +151,7 @@ class Sparc32Linux : public SparcLinux
uint32_t __unused4;
uint32_t __unused5;
} tgt_stat64;
typedef struct {
int32_t uptime; /* Seconds since boot */
uint32_t loads[3]; /* 1, 5, and 15 minute load averages */
@@ -165,7 +165,7 @@ class Sparc32Linux : public SparcLinux
uint32_t totalhigh; /* Total high memory size */
uint32_t freehigh; /* Available high memory size */
uint32_t mem_unit; /* Memory unit size in bytes */
} tgt_sysinfo;
} tgt_sysinfo;
/// Resource constants for getrlimit() (overide some generics).
static const unsigned TGT_RLIMIT_NPROC = 7;

2
src/arch/sparc/pagetable.hh
View File

@@ -57,7 +57,7 @@ class TteTag
TteTag(uint64_t e) : entry(e), populated(true) {}
const TteTag &
operator=(uint64_t e)
operator=(uint64_t e)
{
populated = true;
entry = e;

2
src/arch/x86/cpuid.cc
View File

@@ -49,7 +49,7 @@ namespace X86ISA {
L2L3CacheAndL2TLB,
APMInfo,
LongModeAddressSize,
/*
* The following are defined by the spec but not yet implemented
*/

2
src/arch/x86/faults.cc
View File

@@ -103,7 +103,7 @@ namespace X86ISA
return ss.str();
}
void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
{
X86FaultBase::invoke(tc);

2
src/arch/x86/insts/micromediaop.hh
View File

@@ -68,7 +68,7 @@ namespace X86ISA
{
return ext & MediaScalarOp;
}
int
numItems(int size) const
{

4
src/arch/x86/isa/insts/general_purpose/system_calls.py
View File

@@ -43,7 +43,7 @@ def macroop SYSCALL_64
# Save the next RIP.
rdip rcx
# Stick rflags with RF masked into r11.
rflags t2
limm t3, "~RFBit", dataSize=8
@@ -96,7 +96,7 @@ def macroop SYSCALL_COMPAT
# Save the next RIP.
rdip rcx
# Stick rflags with RF masked into r11.
rflags t2
limm t3, "~RFBit", dataSize=8

8
src/arch/x86/isa/insts/romutil.py
View File

@@ -66,7 +66,7 @@ def rom
wrdh t9, t4, t2, dataSize=8
#
#
# Figure out where the stack should be
#
@@ -74,7 +74,7 @@ def rom
rdsel t11, ss
# Check if we're changing privelege level. At this point we can assume
# we're going to a DPL that's less than or equal to the CPL.
# we're going to a DPL that's less than or equal to the CPL.
rdattr t10, hs, dataSize=8
andi t10, t10, 3, dataSize=8
rdattr t5, cs, dataSize=8
@@ -139,7 +139,7 @@ def rom
# Build up the interrupt stack frame
#
# Write out the contents of memory
%(errorCodeCode)s
st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8
@@ -173,7 +173,7 @@ def rom
# Put the results into rflags
wrflags t6, t10
eret
};
'''

2
src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
View File

@@ -50,7 +50,7 @@ def macroop MOVD_MMX_P {
};
def macroop MOVD_R_MMX {
mov2int reg, mmxm, size=dsz
mov2int reg, mmxm, size=dsz
};
def macroop MOVD_M_MMX {

2
src/arch/x86/isa/microops/base.isa
View File

@@ -51,7 +51,7 @@ let {{
let {{
class X86Microop(object):
generatorNameTemplate = "generate_%s_%d"
generatorTemplate = '''

10
src/arch/x86/isa/microops/mediaop.isa
View File

@@ -214,7 +214,7 @@ let {{
if ext is None:
self.ext = 0
else:
self.ext = ext
self.ext = ext
def getAllocator(self, microFlags):
className = self.className
@@ -926,7 +926,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits + arg2Bits;
if (ext & 0x2) {
if (signedOp()) {
int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -963,7 +963,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits - arg2Bits;
if (ext & 0x2) {
if (signedOp()) {
int arg1Sign = bits(arg1Bits, sizeBits - 1);
@@ -1025,7 +1025,7 @@ let {{
if (ext & 0x4)
resBits += (ULL(1) << (destBits - 1));
if (multHi())
resBits >>= destBits;
@@ -1050,7 +1050,7 @@ let {{
uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
result = insertBits(result, hiIndex, loIndex, resBits);
}
FpDestReg_uqw = result;

6
src/arch/x86/isa/microops/regop.isa
View File

@@ -238,7 +238,7 @@ let {{
global exec_output
# Stick all the code together so it can be searched at once
allCode = "|".join((code, flag_code, cond_check, else_code,
allCode = "|".join((code, flag_code, cond_check, else_code,
cond_control_flag_init))
allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
cond_control_flag_init))
@@ -786,7 +786,7 @@ let {{
PredecfBit = PredecfBit & ~(ext & ECFBit);
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
if ((ext & (CFBit | ECFBit)) &&
shiftAmt <= dataSize * 8 &&
bits(SrcReg1, shiftAmt - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -1018,7 +1018,7 @@ let {{
int msb = bits(DestReg, dataSize * 8 - 1);
int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
if ((ext & (CFBit | ECFBit)) &&
(realShiftAmt == 0) ? origCFBit : CFBits) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);

2
src/arch/x86/process.cc
View File

@@ -612,7 +612,7 @@ I386LiveProcess::initState()
argsInit(sizeof(uint32_t), PageBytes);
/*
/*
* Set up a GDT for this process. The whole GDT wouldn't really be for
* this process, but the only parts we care about are.
*/

2
src/arch/x86/process.hh
View File

@@ -74,7 +74,7 @@ namespace X86ISA
public:
Addr gdtStart()
{ return _gdtStart; }
Addr gdtSize()
{ return _gdtSize; }