ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system configuration code can be shared by multiple front-end configuration files (i.e. memory tester, full system, and hopefully the regression tester). This code works for memory tester, but have not tested fs mode.
This commit is contained in:
Brad Beckmann
117
configs/ruby/MOESI_hammer.py
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117
configs/ruby/MOESI_hammer.py
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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assoc = 2
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latency = 3
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size = 32768
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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assoc = 16
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latency = 15
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size = 1048576
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def create_system(options, physmem):
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if buildEnv['PROTOCOL'] != 'MOESI_hammer':
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panic("This script requires the MOESI_hammer protocol to be built.")
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sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in range(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Eventually this code should go in a python file specific to the
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# MOESI_hammer protocol
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#
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l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
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l1i_cache = L1Cache(cache_profiler = l1i_profiler)
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l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i))
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l1d_cache = L1Cache(cache_profiler = l1d_profiler)
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l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i))
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l2_cache = L2Cache(cache_profiler = l2_profiler)
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cpu_seq = RubySequencer(icache = l1i_cache,
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dcache = l1d_cache,
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funcmem_port = physmem.port)
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L2cacheMemory = l2_cache)
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mem_cntrl = RubyMemoryControl(version = i)
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dir_cntrl = Directory_Controller(version = i,
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directory = RubyDirectoryMemory(),
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memBuffer = mem_cntrl)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = DMASequencer())
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#
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# Add controllers and sequencers to the appropriate lists
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# As noted above: Independent list are track to maintain the order of
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# nodes/controllers assumed by the ruby network
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#
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sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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return (sequencers, dir_cntrl_nodes, all_cntrls)
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82
configs/ruby/Ruby.py
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82
configs/ruby/Ruby.py
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@@ -0,0 +1,82 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import MOESI_hammer
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def create_system(options, physmem):
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protocol = buildEnv['PROTOCOL']
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if protocol == "MOESI_hammer":
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(sequencers, dir_cntrls, all_cntrls) = MOESI_hammer.create_system( \
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options, physmem)
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else:
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print "Error: unsupported ruby protocol"
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sys.exit(1)
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#
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# Important: the topology constructor must be called before the network
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# constructor.
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#
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network = SimpleNetwork(topology = makeCrossbar(all_cntrls))
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mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
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for dir_cntrl in dir_cntrls])
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#
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# determine the number of memory controllers and other memory controller
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# parameters for the profiler
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#
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mcCount = len(dir_cntrls)
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banksPerRank = dir_cntrls[0].memBuffer.banks_per_rank
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ranksPerDimm = dir_cntrls[0].memBuffer.ranks_per_dimm
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dimmsPerChannel = dir_cntrls[0].memBuffer.dimms_per_channel
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ruby_profiler = RubyProfiler(mem_cntrl_count = mcCount,
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banks_per_rank = banksPerRank,
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ranks_per_dimm = ranksPerDimm,
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dimms_per_channel = dimmsPerChannel)
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ruby = RubySystem(clock = '1GHz',
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network = network,
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profiler = ruby_profiler,
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tracer = RubyTracer(),
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debug = RubyDebug(filter_string = 'none',
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verbosity_string = 'none',
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protocol_trace = False),
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mem_size_mb = mem_size_mb)
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ruby.cpu_ruby_ports = sequencers
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return ruby
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