x86, mem: Rewrite the multilevel page table class.
The new version extracts all the x86 specific aspects of the class, and builds the interface around a variable collection of template arguments which are classes that represent the different levels of the page table. The multilevel page table class is now much more ISA independent. Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636 Reviewed-on: https://gem5-review.googlesource.com/7347 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
@@ -63,39 +63,6 @@ typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
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namespace X86ISA
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{
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BitUnion64(VAddr)
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Bitfield<20, 12> longl1;
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Bitfield<29, 21> longl2;
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Bitfield<38, 30> longl3;
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Bitfield<47, 39> longl4;
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Bitfield<20, 12> pael1;
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Bitfield<29, 21> pael2;
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Bitfield<31, 30> pael3;
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Bitfield<21, 12> norml1;
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Bitfield<31, 22> norml2;
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EndBitUnion(VAddr)
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// Unfortunately, the placement of the base field in a page table entry is
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// very erratic and would make a mess here. It might be moved here at some
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// point in the future.
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BitUnion64(PageTableEntry)
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Bitfield<63> nx;
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Bitfield<51, 12> base;
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Bitfield<11, 9> avl;
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Bitfield<8> g;
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Bitfield<7> ps;
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Bitfield<6> d;
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Bitfield<5> a;
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Bitfield<4> pcd;
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Bitfield<3> pwt;
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Bitfield<2> u;
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Bitfield<1> w;
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Bitfield<0> p;
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EndBitUnion(PageTableEntry)
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struct TlbEntry : public Serializable
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{
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// The base of the physical page.
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@@ -152,65 +119,87 @@ namespace X86ISA
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void unserialize(CheckpointIn &cp) override;
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};
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/** The size of each level of the page table expressed in base 2
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* logarithmic values
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*/
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const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
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/* x86 specific PTE flags */
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enum PTEField{
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PTE_NotPresent = 1,
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PTE_Supervisor = 2,
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PTE_ReadOnly = 4,
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PTE_Uncacheable = 8,
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};
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BitUnion64(VAddr)
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Bitfield<20, 12> longl1;
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Bitfield<29, 21> longl2;
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Bitfield<38, 30> longl3;
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Bitfield<47, 39> longl4;
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/** Page table operations specific to x86 ISA.
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* Indended to be used as parameter of MultiLevelPageTable.
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*/
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class PageTableOps
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Bitfield<20, 12> pael1;
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Bitfield<29, 21> pael2;
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Bitfield<31, 30> pael3;
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Bitfield<21, 12> norml1;
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Bitfield<31, 22> norml2;
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EndBitUnion(VAddr)
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// Unfortunately, the placement of the base field in a page table entry is
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// very erratic and would make a mess here. It might be moved here at some
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// point in the future.
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BitUnion64(PageTableEntry)
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Bitfield<63> nx;
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Bitfield<51, 12> base;
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Bitfield<11, 9> avl;
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Bitfield<8> g;
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Bitfield<7> ps;
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Bitfield<6> d;
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Bitfield<5> a;
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Bitfield<4> pcd;
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Bitfield<3> pwt;
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Bitfield<2> u;
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Bitfield<1> w;
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Bitfield<0> p;
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EndBitUnion(PageTableEntry)
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template <int first, int last>
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class LongModePTE
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{
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public:
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void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0)
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Addr paddr() { return pte.base << PageShift; }
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void paddr(Addr addr) { pte.base = addr >> PageShift; }
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bool present() { return pte.p; }
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void present(bool p) { pte.p = p ? 1 : 0; }
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bool uncacheable() { return pte.pcd; }
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void uncacheable(bool u) { pte.pcd = u ? 1 : 0; }
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bool readonly() { return !pte.w; }
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void readonly(bool r) { pte.w = r ? 0 : 1; }
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void
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read(PortProxy &p, Addr table, Addr vaddr)
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{
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PTE.p = flags & PTE_NotPresent ? 0 : 1;
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PTE.pcd = flags & PTE_Uncacheable ? 1 : 0;
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PTE.w = flags & PTE_ReadOnly ? 0 : 1;
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PTE.u = flags & PTE_Supervisor ? 0 : 1;
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entryAddr = table;
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entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
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pte = p.read<PageTableEntry>(entryAddr);
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}
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/** returns the page number out of a page table entry */
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Addr getPnum(PageTableEntry PTE)
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void
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reset(Addr _paddr, bool _present=true,
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bool _uncacheable=false, bool _readonly=false)
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{
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return PTE.base;
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pte = 0;
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pte.u = 1;
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paddr(_paddr);
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present(_present);
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uncacheable(_uncacheable);
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readonly(_readonly);
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};
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void write(PortProxy &p) { p.write(entryAddr, pte); }
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static int
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tableSize()
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{
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return 1 << ((first - last) + 4 - PageShift);
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}
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bool isUncacheable(const PageTableEntry PTE)
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{
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return PTE.pcd;
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}
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bool isReadOnly(PageTableEntry PTE)
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{
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return !PTE.w;
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}
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/** sets the page number in a page table entry */
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void setPnum(PageTableEntry& PTE, Addr paddr)
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{
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PTE.base = paddr;
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}
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/** returns the offsets to index in every level of a page
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* table, contained in a virtual address
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*/
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std::vector<uint64_t> getOffsets(Addr vaddr)
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{
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X86ISA::VAddr addr(vaddr);
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return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
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}
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protected:
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PageTableEntry pte;
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Addr entryAddr;
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};
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}
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#endif
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@@ -96,14 +96,21 @@ static const int ArgumentReg32[] = {
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static const int NumArgumentRegs32 M5_VAR_USED =
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sizeof(ArgumentReg) / sizeof(const int);
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template class MultiLevelPageTable<LongModePTE<47, 39>,
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LongModePTE<38, 30>,
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LongModePTE<29, 21>,
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LongModePTE<20, 12> >;
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typedef MultiLevelPageTable<LongModePTE<47, 39>,
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LongModePTE<38, 30>,
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LongModePTE<29, 21>,
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LongModePTE<20, 12> > ArchPageTable;
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X86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
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SyscallDesc *_syscallDescs, int _numSyscallDescs)
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: Process(params, params->useArchPT ?
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static_cast<EmulationPageTable *>(
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new ArchPageTable(
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params->name, params->pid,
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params->system, PageBytes,
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PageTableLayout)) :
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new ArchPageTable(params->name, params->pid,
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params->system, PageBytes)) :
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new EmulationPageTable(params->name, params->pid,
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PageBytes),
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objFile),
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@@ -543,23 +550,22 @@ X86_64Process::initState()
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physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
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MultiLevelPageTable<PageTableOps> *pt =
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dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
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/* Syscall handler */
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pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
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pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
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PageBytes, false);
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/* GDT */
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pt->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
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pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
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/* IDT */
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pt->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
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pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
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/* TSS */
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pt->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
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pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
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/* IST */
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pt->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
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pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
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/* PF handler */
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pt->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
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pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
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/* MMIO region for m5ops */
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pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
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pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
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16 * PageBytes, false);
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} else {
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for (int i = 0; i < contextIds.size(); i++) {
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ThreadContext * tc = system->getThreadContext(contextIds[i]);
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@@ -43,6 +43,7 @@
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#include <string>
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#include <vector>
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#include "arch/x86/pagetable.hh"
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#include "mem/multi_level_page_table.hh"
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#include "sim/aux_vector.hh"
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#include "sim/process.hh"
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@@ -65,7 +66,6 @@ namespace X86ISA
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* These page tables are stored in system memory and respect x86
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* specification.
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*/
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typedef MultiLevelPageTable<PageTableOps> ArchPageTable;
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Addr _gdtStart;
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Addr _gdtSize;
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