derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

misc: Replace std::conditional with std::conditional_t

Browse Source 
Change-Id: I50d26d958d521c30b69d31426380b1e2e213a9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44506
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-04-14 13:04:15 +01:00
parent 8e5e603041
commit dabb0c8f45
4 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/amdgpu/vega/operand.hh
View File

@@ -326,12 +326,12 @@ namespace VegaISA
scRegData.read();
}
using VecRegCont = typename std::conditional<NumDwords == 2,
VecRegContainerU64, typename std::conditional<sizeof(DataType)
using VecRegCont = typename std::conditional_t<NumDwords == 2,
VecRegContainerU64, typename std::conditional_t<sizeof(DataType)
== sizeof(VecElemU16), VecRegContainerU16,
typename std::conditional<sizeof(DataType)
typename std::conditional_t<sizeof(DataType)
== sizeof(VecElemU8), VecRegContainerU8,
VecRegContainerU32>::type>::type>::type;
VecRegContainerU32>>>;
/**
* whether this operand a scalar or not.