Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.
I could use some better python magic in the cpu_models.py file!
AUTHORS:
add middle initial
SConstruct:
change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...
Actually, some Python expertise could be used here. The 'env' variable is not
passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
use isa_specific.hh
src/sim/process.cc:
only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
include paths
src/cpu/o3/alpha/impl.hh:
include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
add O3CPU class
src/cpu/o3/SConscript:
include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
new home of AlphaTC
src/cpu/o3/isa_specific.hh:
includes ISA specific files
src/cpu/o3/params.hh:
base o3 params
src/cpu/o3/thread_context.hh:
base o3 thread context
src/cpu/o3/thread_context_impl.hh:
base o3 thead context impl
--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
This commit is contained in:
Korey Sewell
98
src/python/m5/objects/O3CPU.py
Normal file
98
src/python/m5/objects/O3CPU.py
Normal file
@@ -0,0 +1,98 @@
|
||||
from m5 import build_env
|
||||
from m5.config import *
|
||||
from BaseCPU import BaseCPU
|
||||
|
||||
class DerivO3CPU(BaseCPU):
|
||||
type = 'DerivO3CPU'
|
||||
activity = Param.Unsigned("Initial count")
|
||||
numThreads = Param.Unsigned("number of HW thread contexts")
|
||||
|
||||
checker = Param.BaseCPU(NULL, "checker")
|
||||
|
||||
cachePorts = Param.Unsigned("Cache Ports")
|
||||
|
||||
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
|
||||
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
|
||||
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
|
||||
"delay")
|
||||
commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
|
||||
fetchWidth = Param.Unsigned("Fetch width")
|
||||
|
||||
renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
|
||||
iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
|
||||
"delay")
|
||||
commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
|
||||
fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
|
||||
decodeWidth = Param.Unsigned("Decode width")
|
||||
|
||||
iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
|
||||
"delay")
|
||||
commitToRenameDelay = Param.Unsigned("Commit to rename delay")
|
||||
decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
|
||||
renameWidth = Param.Unsigned("Rename width")
|
||||
|
||||
commitToIEWDelay = Param.Unsigned("Commit to "
|
||||
"Issue/Execute/Writeback delay")
|
||||
renameToIEWDelay = Param.Unsigned("Rename to "
|
||||
"Issue/Execute/Writeback delay")
|
||||
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
|
||||
"to the IEW stage)")
|
||||
issueWidth = Param.Unsigned("Issue width")
|
||||
executeWidth = Param.Unsigned("Execute width")
|
||||
executeIntWidth = Param.Unsigned("Integer execute width")
|
||||
executeFloatWidth = Param.Unsigned("Floating point execute width")
|
||||
executeBranchWidth = Param.Unsigned("Branch execute width")
|
||||
executeMemoryWidth = Param.Unsigned("Memory execute width")
|
||||
fuPool = Param.FUPool(NULL, "Functional Unit pool")
|
||||
|
||||
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
|
||||
"delay")
|
||||
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
|
||||
commitWidth = Param.Unsigned("Commit width")
|
||||
squashWidth = Param.Unsigned("Squash width")
|
||||
trapLatency = Param.Tick("Trap latency")
|
||||
fetchTrapLatency = Param.Tick("Fetch trap latency")
|
||||
|
||||
predType = Param.String("Branch predictor type ('local', 'tournament')")
|
||||
localPredictorSize = Param.Unsigned("Size of local predictor")
|
||||
localCtrBits = Param.Unsigned("Bits per counter")
|
||||
localHistoryTableSize = Param.Unsigned("Size of local history table")
|
||||
localHistoryBits = Param.Unsigned("Bits for the local history")
|
||||
globalPredictorSize = Param.Unsigned("Size of global predictor")
|
||||
globalCtrBits = Param.Unsigned("Bits per counter")
|
||||
globalHistoryBits = Param.Unsigned("Bits of history")
|
||||
choicePredictorSize = Param.Unsigned("Size of choice predictor")
|
||||
choiceCtrBits = Param.Unsigned("Bits of choice counters")
|
||||
|
||||
BTBEntries = Param.Unsigned("Number of BTB entries")
|
||||
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
|
||||
|
||||
RASSize = Param.Unsigned("RAS size")
|
||||
|
||||
LQEntries = Param.Unsigned("Number of load queue entries")
|
||||
SQEntries = Param.Unsigned("Number of store queue entries")
|
||||
LFSTSize = Param.Unsigned("Last fetched store table size")
|
||||
SSITSize = Param.Unsigned("Store set ID table size")
|
||||
|
||||
numRobs = Param.Unsigned("Number of Reorder Buffers");
|
||||
|
||||
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
|
||||
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
|
||||
"registers")
|
||||
numIQEntries = Param.Unsigned("Number of instruction queue entries")
|
||||
numROBEntries = Param.Unsigned("Number of reorder buffer entries")
|
||||
|
||||
instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
|
||||
|
||||
function_trace = Param.Bool(False, "Enable function trace")
|
||||
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||
|
||||
smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
|
||||
smtFetchPolicy = Param.String("SMT Fetch policy")
|
||||
smtLSQPolicy = Param.String("SMT LSQ Sharing Policy")
|
||||
smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
|
||||
smtIQPolicy = Param.String("SMT IQ Sharing Policy")
|
||||
smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
|
||||
smtROBPolicy = Param.String("SMT ROB Sharing Policy")
|
||||
smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
|
||||
smtCommitPolicy = Param.String("SMT Commit Policy")
|
||||
Reference in New Issue
Block a user