diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
index 31fb5e8e92..39812e008e 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -66,8 +66,7 @@ class Message
         : m_block_size(block_size),
           m_time(curTime),
           m_LastEnqueueTime(curTime),
-          m_DelayedTicks(0), m_msg_counter(0),
-          p_ruby_system(rs)
+          m_DelayedTicks(0), m_msg_counter(0)
     { }
 
     Message(const Message &other) = default;
@@ -135,9 +134,6 @@ class Message
     // Variables for required network traversal
     int incoming_link;
     int vnet;
-
-    // Needed to call MacheinType_base_count/level
-    const RubySystem *p_ruby_system = nullptr;
 };
 
 inline bool
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
index ecc984a617..ef0365672d 100644
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -51,7 +51,6 @@ class BankedArray
     Tick clockPeriod = 0;
     unsigned int bankBits;
     unsigned int startIndexBit;
-    RubySystem *m_ruby_system;
 
     class AccessRecord
     {