tests: Add checkpoint tests for all ISAs (#167)
Added save and restore checkpoint tests for arm-hello, x86-hello, x86-fs, power-hello Added mips and sparc test but mips does not support checkpoint and there is a bug in sparc. Added test file to run the tests.
This commit is contained in:
Bobby R. Bruce
11
tests/gem5/checkpoint_tests/README.md
Normal file
11
tests/gem5/checkpoint_tests/README.md
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@@ -0,0 +1,11 @@
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# Checkpoint tests
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These tests run hello world binary for arm, x86, and power isa and ubuntuboot workload for x86 isa using checkpoints.
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Each binary is run in two parts:
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- Save checkpoint: A binary is run for a set amount of ticks and then a checkpoint is taken. This test checks if the checkpoint is taken.
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- Resotre checkpoint: The same binary and board in the respective save test are used with the saved checkpoint (the checkpoint is uploaded to gem5 resources). This test checks if the binary ran properly.
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```bash
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./main.py run gem5/checkpoint_tests/
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```
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@@ -0,0 +1,80 @@
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# Copyright (c) 2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
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"""
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This gem5 configuation script creates a simple board sharing the same
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structure as the one in
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tests/gem5/checkpoint-tests/arm-hello-save-checkpoint.py.
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This script restores the checkpoint generated by the above script, and
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runs the rest of "arm-hello64-static" binary simulation.
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This configuration serves as a test of restoring a checkpoint with ARM ISA.
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"""
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import obtain_resource, CheckpointResource
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
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PrivateL1PrivateL2CacheHierarchy,
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)
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.simulate.simulator import Simulator
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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requires(isa_required=ISA.ARM)
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cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
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l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
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)
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memory = SingleChannelDDR3_1600(size="32MB")
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processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)
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board = SimpleBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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board.set_se_binary_workload(
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obtain_resource("arm-hello64-static"),
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checkpoint=obtain_resource("arm-hello-test-checkpoint"),
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)
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sim = Simulator(board=board, full_system=False)
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sim.run()
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print(
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"Exiting @ tick {} because {}.".format(
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sim.get_current_tick(), sim.get_last_exit_event_cause()
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)
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)
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@@ -0,0 +1,77 @@
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# Copyright (c) 2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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import argparse
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import obtain_resource
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
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PrivateL1PrivateL2CacheHierarchy,
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)
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.simulate.simulator import Simulator
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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parser = argparse.ArgumentParser()
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parser.add_argument(
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"--checkpoint-path",
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type=str,
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required=False,
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default="arm-hello-test-checkpoint/",
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help="The directory to store the checkpoint.",
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)
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args = parser.parse_args()
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requires(isa_required=ISA.ARM)
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cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
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l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
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)
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memory = SingleChannelDDR3_1600(size="32MB")
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processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)
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board = SimpleBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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board.set_se_binary_workload(obtain_resource("arm-hello64-static"))
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sim = Simulator(board=board, full_system=False)
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max_ticks = 10**6
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sim.run(max_ticks=max_ticks)
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print(
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"Exiting @ tick {} because {}.".format(
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sim.get_current_tick(), sim.get_last_exit_event_cause()
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)
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)
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print("Taking checkpoint at", args.checkpoint_path)
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sim.save_checkpoint(args.checkpoint_path)
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print("Done taking checkpoint")
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@@ -0,0 +1,72 @@
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# Copyright (c) 2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
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"""
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This gem5 configuation script creates a simple board sharing the same
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structure as the one in
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tests/gem5/checkpoint-tests/power-hello-save-checkpoint.py.
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This script restores the checkpoint generated by the above script, and
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runs the rest of "power-hello" binary simulation.
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This configuration serves as a test of restoring a checkpoint with POWER ISA.
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"""
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import obtain_resource, CheckpointResource
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.simulate.simulator import Simulator
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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requires(isa_required=ISA.POWER)
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cache_hierarchy = NoCache()
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memory = SingleChannelDDR3_1600(size="32MB")
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
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)
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board = SimpleBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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board.set_se_binary_workload(
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obtain_resource("power-hello"),
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checkpoint=obtain_resource("power-hello-test-checkpoint"),
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)
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sim = Simulator(board=board, full_system=False)
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sim.run()
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print(
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"Exiting @ tick {} because {}.".format(
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sim.get_current_tick(), sim.get_last_exit_event_cause()
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)
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)
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@@ -0,0 +1,83 @@
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# Copyright (c) 2023 The Regents of the University of California
|
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# All rights reserved.
|
||||
#
|
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
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"""
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This gem5 test script creates a simple board to run the first
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10^6 ticks of "power-hello" binary simulation and saves a checkpoint.
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This configuration serves as a test to ensure that checkpoints work
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with POWER ISA.
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"""
|
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|
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import argparse
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from gem5.isas import ISA
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from gem5.utils.requires import requires
|
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from gem5.resources.resource import obtain_resource
|
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
|
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from gem5.components.boards.simple_board import SimpleBoard
|
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from gem5.components.processors.simple_processor import SimpleProcessor
|
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from gem5.simulate.simulator import Simulator
|
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from gem5.components.memory import SingleChannelDDR3_1600
|
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from gem5.components.processors.cpu_types import CPUTypes
|
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|
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parser = argparse.ArgumentParser()
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|
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parser.add_argument(
|
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"--checkpoint-path",
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type=str,
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required=False,
|
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default="power-hello-test-checkpoint/",
|
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help="The directory to store the checkpoint.",
|
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)
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args = parser.parse_args()
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requires(isa_required=ISA.POWER)
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cache_hierarchy = NoCache()
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memory = SingleChannelDDR3_1600(size="32MB")
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
|
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)
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board = SimpleBoard(
|
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
|
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)
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board.set_se_binary_workload(obtain_resource("power-hello"))
|
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sim = Simulator(board=board, full_system=False)
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max_ticks = 10**6
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sim.run(max_ticks=max_ticks)
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print(
|
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"Exiting @ tick {} because {}.".format(
|
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sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
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print("Taking checkpoint at", args.checkpoint_path)
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sim.save_checkpoint(args.checkpoint_path)
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print("Done taking checkpoint")
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@@ -0,0 +1,72 @@
|
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# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 configuation script creates a simple board sharing the same
|
||||
structure as the one in
|
||||
tests/gem5/checkpoint-tests/sparc-hello-save-checkpoint.py.
|
||||
This script restores the checkpoint generated by the above script, and
|
||||
runs the rest of "sparc-hello" binary simulation.
|
||||
This configuration serves as a test of restoring a checkpoint with SPARC ISA.
|
||||
"""
|
||||
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource, CheckpointResource
|
||||
from gem5.components.cachehierarchies.classic.no_cache import NoCache
|
||||
from gem5.components.boards.simple_board import SimpleBoard
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.simulate.simulator import Simulator
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
|
||||
|
||||
requires(isa_required=ISA.SPARC)
|
||||
|
||||
cache_hierarchy = NoCache()
|
||||
|
||||
memory = SingleChannelDDR3_1600(size="32MB")
|
||||
processor = SimpleProcessor(
|
||||
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
|
||||
)
|
||||
board = SimpleBoard(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
board.set_se_binary_workload(
|
||||
obtain_resource("sparc-hello"),
|
||||
checkpoint=CheckpointResource(local_path="./sparc-hello-test-checkpoint"),
|
||||
)
|
||||
|
||||
sim = Simulator(board=board, full_system=False)
|
||||
sim.run()
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,83 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 test script creates a simple board to run the first
|
||||
10^6 ticks of "sparc-hello" binary simulation and saves a checkpoint.
|
||||
This configuration serves as a test to ensure that checkpoints work
|
||||
with SPARC ISA.
|
||||
"""
|
||||
|
||||
import argparse
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource
|
||||
from gem5.components.cachehierarchies.classic.no_cache import NoCache
|
||||
from gem5.components.boards.simple_board import SimpleBoard
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.simulate.simulator import Simulator
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
|
||||
parser = argparse.ArgumentParser()
|
||||
|
||||
parser.add_argument(
|
||||
"--checkpoint-path",
|
||||
type=str,
|
||||
required=False,
|
||||
default="sparc-hello-test-checkpoint/",
|
||||
help="The directory to store the checkpoint.",
|
||||
)
|
||||
|
||||
args = parser.parse_args()
|
||||
requires(isa_required=ISA.SPARC)
|
||||
|
||||
cache_hierarchy = NoCache()
|
||||
|
||||
memory = SingleChannelDDR3_1600(size="32MB")
|
||||
processor = SimpleProcessor(
|
||||
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
|
||||
)
|
||||
|
||||
board = SimpleBoard(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
board.set_se_binary_workload(obtain_resource("sparc-hello"))
|
||||
|
||||
sim = Simulator(board=board, full_system=False)
|
||||
max_ticks = 10**6
|
||||
sim.run(max_ticks=max_ticks)
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
print("Taking checkpoint at", args.checkpoint_path)
|
||||
sim.save_checkpoint(args.checkpoint_path)
|
||||
print("Done taking checkpoint")
|
||||
@@ -0,0 +1,88 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 configuation script creates a simple board sharing the same
|
||||
structure as the one in
|
||||
tests/gem5/checkpoint-tests/x86-fs-save-checkpoint.py.
|
||||
This script restores the checkpoint generated by the above script, and
|
||||
runs the rest of full system simulation.
|
||||
This configuration serves as a test of restoring a checkpoint with X86 ISA in fs mode.
|
||||
"""
|
||||
|
||||
from gem5.components.boards.x86_board import X86Board
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
|
||||
PrivateL1PrivateL2CacheHierarchy,
|
||||
)
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource, CheckpointResource
|
||||
from gem5.simulate.simulator import Simulator
|
||||
|
||||
# Run a check to ensure the right version of gem5 is being used.
|
||||
requires(isa_required=ISA.X86)
|
||||
|
||||
# Setup the cache hierarchy.
|
||||
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
|
||||
# For Ruby, MESI_Two_Level and MI_example have been tested.
|
||||
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
|
||||
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
|
||||
)
|
||||
|
||||
# Setup the system memory.
|
||||
memory = SingleChannelDDR3_1600(size="1GB")
|
||||
|
||||
# Setup a single core Processor.
|
||||
processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)
|
||||
|
||||
# Setup the board.
|
||||
board = X86Board(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
|
||||
# Set the Full System workload.
|
||||
board.set_kernel_disk_workload(
|
||||
kernel=obtain_resource("x86-linux-kernel-5.4.49"),
|
||||
disk_image=obtain_resource("x86-ubuntu-18.04-img"),
|
||||
checkpoint=obtain_resource("x86-fs-test-checkpoint"),
|
||||
)
|
||||
|
||||
sim = Simulator(board=board, full_system=True)
|
||||
print("Beginning simulation!")
|
||||
|
||||
sim.run(max_ticks=10**10)
|
||||
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
101
tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py
Normal file
101
tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py
Normal file
@@ -0,0 +1,101 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 test script creates a simple board to run the first
|
||||
10^6 ticks of x86 full system kernel disk workload simulation and saves a checkpoint.
|
||||
This configuration serves as a test to ensure that checkpoints work
|
||||
with X86 ISA in fs mode.
|
||||
"""
|
||||
|
||||
import argparse
|
||||
from gem5.components.boards.x86_board import X86Board
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
|
||||
PrivateL1PrivateL2CacheHierarchy,
|
||||
)
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource
|
||||
from gem5.simulate.simulator import Simulator
|
||||
|
||||
parser = argparse.ArgumentParser()
|
||||
|
||||
parser.add_argument(
|
||||
"--checkpoint-path",
|
||||
type=str,
|
||||
required=False,
|
||||
default="x86-fs-test-checkpoint/",
|
||||
help="The directory to store the checkpoint.",
|
||||
)
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
# Run a check to ensure the right version of gem5 is being used.
|
||||
requires(isa_required=ISA.X86)
|
||||
|
||||
# Setup the cache hierarchy.
|
||||
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
|
||||
# For Ruby, MESI_Two_Level and MI_example have been tested.
|
||||
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
|
||||
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
|
||||
)
|
||||
|
||||
# Setup the system memory.
|
||||
memory = SingleChannelDDR3_1600(size="1GB")
|
||||
|
||||
# Setup a single core Processor.
|
||||
processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)
|
||||
|
||||
# Setup the board.
|
||||
board = X86Board(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
|
||||
# Set the Full System workload.
|
||||
board.set_kernel_disk_workload(
|
||||
kernel=obtain_resource("x86-linux-kernel-5.4.49"),
|
||||
disk_image=obtain_resource("x86-ubuntu-18.04-img"),
|
||||
)
|
||||
|
||||
sim = Simulator(board=board, full_system=True)
|
||||
print("Beginning simulation!")
|
||||
|
||||
max_ticks = 10**6
|
||||
sim.run(max_ticks=max_ticks)
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
print("Taking checkpoint at", args.checkpoint_path)
|
||||
sim.save_checkpoint(args.checkpoint_path)
|
||||
print("Done taking checkpoint")
|
||||
@@ -0,0 +1,72 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 configuation script creates a simple board sharing the same
|
||||
structure as the one in
|
||||
tests/gem5/checkpoint-tests/x86-hello-save-checkpoint.py.
|
||||
This script restores the checkpoint generated by the above script, and
|
||||
runs the rest of "x86-hello64-static" binary simulation.
|
||||
This configuration serves as a test of restoring a checkpoint with X86 ISA.
|
||||
"""
|
||||
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource, CheckpointResource
|
||||
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
|
||||
PrivateL1CacheHierarchy,
|
||||
)
|
||||
from gem5.components.boards.simple_board import SimpleBoard
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.simulate.simulator import Simulator
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
|
||||
|
||||
requires(isa_required=ISA.X86)
|
||||
|
||||
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
|
||||
|
||||
memory = SingleChannelDDR3_1600(size="32MB")
|
||||
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
|
||||
board = SimpleBoard(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
board.set_se_binary_workload(
|
||||
obtain_resource("x86-hello64-static"),
|
||||
checkpoint=obtain_resource("x86-hello-test-checkpoint"),
|
||||
)
|
||||
|
||||
sim = Simulator(board=board, full_system=False)
|
||||
sim.run()
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,83 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This gem5 test script creates a simple board to run the first
|
||||
10^6 ticks of "x86-hello64-static" binary simulation and saves a checkpoint.
|
||||
This configuration serves as a test to ensure that checkpoints work
|
||||
with X86 ISA.
|
||||
"""
|
||||
|
||||
import argparse
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.resources.resource import obtain_resource
|
||||
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
|
||||
PrivateL1CacheHierarchy,
|
||||
)
|
||||
from gem5.components.boards.simple_board import SimpleBoard
|
||||
from gem5.components.processors.simple_processor import SimpleProcessor
|
||||
from gem5.simulate.simulator import Simulator
|
||||
from gem5.components.memory import SingleChannelDDR3_1600
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
|
||||
parser = argparse.ArgumentParser()
|
||||
|
||||
parser.add_argument(
|
||||
"--checkpoint-path",
|
||||
type=str,
|
||||
required=False,
|
||||
default="x86-hello-test-checkpoint/",
|
||||
help="The directory to store the checkpoint.",
|
||||
)
|
||||
|
||||
args = parser.parse_args()
|
||||
requires(isa_required=ISA.X86)
|
||||
|
||||
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
|
||||
|
||||
memory = SingleChannelDDR3_1600(size="32MB")
|
||||
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
|
||||
|
||||
board = SimpleBoard(
|
||||
clk_freq="3GHz",
|
||||
processor=processor,
|
||||
memory=memory,
|
||||
cache_hierarchy=cache_hierarchy,
|
||||
)
|
||||
board.set_se_binary_workload(obtain_resource("x86-hello64-static"))
|
||||
|
||||
sim = Simulator(board=board, full_system=False)
|
||||
max_ticks = 10**6
|
||||
sim.run(max_ticks=max_ticks)
|
||||
print(
|
||||
"Exiting @ tick {} because {}.".format(
|
||||
sim.get_current_tick(), sim.get_last_exit_event_cause()
|
||||
)
|
||||
)
|
||||
print("Taking checkpoint at", args.checkpoint_path)
|
||||
sim.save_checkpoint(args.checkpoint_path)
|
||||
print("Done taking checkpoint")
|
||||
241
tests/gem5/checkpoint_tests/test-checkpoints.py
Normal file
241
tests/gem5/checkpoint_tests/test-checkpoints.py
Normal file
@@ -0,0 +1,241 @@
|
||||
# Copyright (c) 2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
"""
|
||||
This runs simple tests to ensure the examples in `configs/example/gem5_library`
|
||||
still function. They simply check the simulation completed.
|
||||
"""
|
||||
from testlib import *
|
||||
import re
|
||||
import os
|
||||
|
||||
if config.bin_path:
|
||||
resource_path = config.bin_path
|
||||
else:
|
||||
resource_path = joinpath(absdirpath(__file__), "..", "resources")
|
||||
|
||||
hello_verifier = verifier.MatchRegex(re.compile(r"Hello world!"))
|
||||
save_checkpoint_verifier = verifier.MatchRegex(
|
||||
re.compile(r"Done taking checkpoint")
|
||||
)
|
||||
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-arm-hello-save-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(save_checkpoint_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"arm-hello-save-checkpoint.py",
|
||||
),
|
||||
config_args=[
|
||||
"--checkpoint-path",
|
||||
joinpath(resource_path, "arm-hello-test-checkpoint"),
|
||||
],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-arm-hello-restore-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(hello_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"arm-hello-restore-checkpoint.py",
|
||||
),
|
||||
config_args=[],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-x86-hello-save-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(save_checkpoint_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"x86-hello-save-checkpoint.py",
|
||||
),
|
||||
config_args=[
|
||||
"--checkpoint-path",
|
||||
joinpath(resource_path, "x86-hello-test-checkpoint"),
|
||||
],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-x86-hello-restore-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(hello_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"x86-hello-restore-checkpoint.py",
|
||||
),
|
||||
config_args=[],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-x86-fs-save-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(save_checkpoint_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"x86-fs-save-checkpoint.py",
|
||||
),
|
||||
config_args=[
|
||||
"--checkpoint-path",
|
||||
joinpath(resource_path, "x86-fs-test-checkpoint"),
|
||||
],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-x86-fs-restore-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"x86-fs-restore-checkpoint.py",
|
||||
),
|
||||
config_args=[],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-power-hello-save-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(save_checkpoint_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"power-hello-save-checkpoint.py",
|
||||
),
|
||||
config_args=[
|
||||
"--checkpoint-path",
|
||||
joinpath(resource_path, "power-hello-test-checkpoint"),
|
||||
],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
gem5_verify_config(
|
||||
name="test-checkpoint-power-hello-restore-checkpoint",
|
||||
fixtures=(),
|
||||
verifiers=(hello_verifier,),
|
||||
config=joinpath(
|
||||
config.base_dir,
|
||||
"tests",
|
||||
"gem5",
|
||||
"checkpoint_tests",
|
||||
"configs",
|
||||
"power-hello-restore-checkpoint.py",
|
||||
),
|
||||
config_args=[],
|
||||
valid_isas=(constants.all_compiled_tag,),
|
||||
valid_hosts=constants.supported_hosts,
|
||||
length=constants.quick_tag,
|
||||
)
|
||||
|
||||
# There is a bug in sparc isa that causes the checkpoints to fail
|
||||
# GitHub issue: https://github.com/gem5/gem5/issues/197
|
||||
# gem5_verify_config(
|
||||
# name="test-checkpoint-sparc-hello-save-checkpoint",
|
||||
# fixtures=(),
|
||||
# verifiers=(save_checkpoint_verifier,),
|
||||
# config=joinpath(
|
||||
# config.base_dir,
|
||||
# "tests",
|
||||
# "gem5",
|
||||
# "checkpoint_tests",
|
||||
# "configs",
|
||||
# "sparc-hello-save-checkpoint.py",
|
||||
# ),
|
||||
# config_args=[
|
||||
# # "--checkpoint-path",
|
||||
# # joinpath(resource_path, "sparc-hello-test-checkpoint"),
|
||||
# ],
|
||||
# valid_isas=(constants.all_compiled_tag,),
|
||||
# valid_hosts=constants.supported_hosts,
|
||||
# length=constants.quick_tag,
|
||||
# )
|
||||
|
||||
# gem5_verify_config(
|
||||
# name="test-checkpoint-sparc-hello-restore-checkpoint",
|
||||
# fixtures=(),
|
||||
# verifiers=(hello_verifier,),
|
||||
# config=joinpath(
|
||||
# config.base_dir,
|
||||
# "tests",
|
||||
# "gem5",
|
||||
# "checkpoint_tests",
|
||||
# "configs",
|
||||
# "sparc-hello-restore-checkpoint.py",
|
||||
# ),
|
||||
# config_args=[],
|
||||
# valid_isas=(constants.all_compiled_tag,),
|
||||
# valid_hosts=constants.supported_hosts,
|
||||
# length=constants.quick_tag,
|
||||
# )
|
||||
Reference in New Issue
Block a user