mem: Add ExternalMaster and ExternalSlave ports

This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.

src/mem/SConscript

@@ -40,6 +40,8 @@ SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('DRAMCtrl.py')
+SimObject('ExternalMaster.py')
+SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
 SimObject('XBar.py')
@@ -50,6 +52,8 @@ Source('bridge.cc')
 Source('coherent_xbar.cc')
 Source('drampower.cc')
 Source('dram_ctrl.cc')
+Source('external_master.cc')
+Source('external_slave.cc')
 Source('mem_object.cc')
 Source('mport.cc')
 Source('noncoherent_xbar.cc')
@@ -88,6 +92,7 @@ DebugFlag('CommMonitor')
 DebugFlag('DRAM')
 DebugFlag('DRAMPower')
 DebugFlag('DRAMState')
+DebugFlag('ExternalPort')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')