config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
This commit is contained in:
Nilay Vaish
@@ -10,6 +10,8 @@
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@@ -37,6 +39,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Brad Beckmann
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import optparse
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import sys
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@@ -47,6 +50,9 @@ from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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import Ruby
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from FSConfig import *
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from SysPaths import *
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@@ -61,6 +67,10 @@ parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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@@ -104,13 +114,14 @@ else:
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np = options.num_cpus
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
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options.ruby)
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
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options.dtb_filename,
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@@ -120,6 +131,9 @@ elif buildEnv['TARGET_ISA'] == "arm":
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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# Set the cache line size for the entire system
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test_sys.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain
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test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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@@ -156,32 +170,72 @@ test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
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if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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if options.ruby:
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
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# Create a seperate clock domain for Ruby
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test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = test_sys.voltage_domain)
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for (i, cpu) in enumerate(test_sys.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = test_sys.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
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cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
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test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
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# Create the appropriate memory controllers and connect them to the
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# PIO bus
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test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
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for i in xrange(len(test_sys.mem_ctrls)):
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test_sys.mem_ctrls[i].port = test_sys.iobus.master
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem:
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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# Sanity check
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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if len(bm) == 2:
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if buildEnv['TARGET_ISA'] == 'alpha':
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