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misc: Remove typedef (struct|enum) Foo in cpp files.

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In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-05-28 21:03:47 -07:00
parent 9b1ff519aa
commit d58b4f004e
23 changed files with 142 additions and 142 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/dev/arm/gic_v3.hh
View File

@@ -81,27 +81,27 @@ class Gicv3 : public BaseGic
static const int PPI_MAX = 16;
// Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
typedef enum
enum IntStatus
{
INT_INACTIVE,
INT_PENDING,
INT_ACTIVE,
INT_ACTIVE_PENDING,
} IntStatus;
};
// Interrupt groups, as per SPEC section 4.6
typedef enum
enum GroupId
{
G0S,
G1S,
G1NS,
} GroupId;
};
typedef enum
enum IntTriggerType
{
INT_LEVEL_SENSITIVE,
INT_EDGE_TRIGGERED,
} IntTriggerType;
};
protected:

4
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -154,12 +154,12 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
typedef struct
struct hppi_t
{
uint32_t intid;
uint8_t prio;
Gicv3::GroupId group;
} hppi_t;
};
hppi_t hppi;

20
src/dev/hsa/hsa_packet.hh
View File

@@ -41,7 +41,7 @@
namespace gem5
{
typedef struct hsa_packet_header_s
struct hsa_packet_header_bitfield_t
{
// TODO: replace with more portable impl based on offset, length
uint16_t type:8;
@@ -49,10 +49,10 @@ typedef struct hsa_packet_header_s
uint16_t acquire_fence_scope:2;
uint16_t release_fence_scope:2;
uint16_t reserved:3;
} hsa_packet_header_bitfield_t;
};
//TODO: put an _ in front of these guys to avoud prob with hsa.h for now
typedef struct _hsa_dispatch_packet_s
struct _hsa_dispatch_packet_t
{
uint16_t header;
uint16_t setup;
@@ -69,9 +69,9 @@ typedef struct _hsa_dispatch_packet_s
uint64_t kernarg_address;
uint64_t reserved1;
uint64_t completion_signal;
} _hsa_dispatch_packet_t;
};
typedef struct _hsa_agent_dispatch_packet_s
struct _hsa_agent_dispatch_packet_t
{
uint16_t header;
uint16_t type;
@@ -80,9 +80,9 @@ typedef struct _hsa_agent_dispatch_packet_s
uint64_t arg[4];
uint64_t reserved2;
uint64_t completion_signal;
} _hsa_agent_dispatch_packet_t;
};
typedef struct _hsa_barrier_and_packet_s
struct _hsa_barrier_and_packet_t
{
uint16_t header;
uint16_t reserved0;
@@ -90,9 +90,9 @@ typedef struct _hsa_barrier_and_packet_s
uint64_t dep_signal[5];
uint64_t reserved2;
uint64_t completion_signal;
} _hsa_barrier_and_packet_t;
};
typedef struct _hsa_barrier_or_packet_s
struct _hsa_barrier_or_packet_t
{
uint16_t header;
uint16_t reserved0;
@@ -100,7 +100,7 @@ typedef struct _hsa_barrier_or_packet_s
uint64_t dep_signal[5];
uint64_t reserved2;
uint64_t completion_signal;
} _hsa_barrier_or_packet_t;
};
} // namespace gem5

15
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -58,7 +58,7 @@ namespace gem5
// Ideally, each queue should store this status and
// the processPkt() should make decisions based on that
// status variable.
typedef enum
enum Q_STATE
{
UNBLOCKED = 0, // Unblocked queue, can submit packets.
BLOCKED_BBIT, // Queue blocked by barrier bit.
@@ -67,7 +67,7 @@ typedef enum
BLOCKED_BPKT, // Queue blocked by barrier packet.
// Can submit packet packets after
// barrier packet completes.
} Q_STATE;
};
class GPUCommandProcessor;
class HWScheduler;
@@ -209,18 +209,17 @@ class AQLRingBuffer
uint64_t compltnPending() { return (_dispIdx - _rdIdx); }
};
typedef struct QueueContext
struct QCntxt
{
HSAQueueDescriptor* qDesc;
AQLRingBuffer* aqlBuf;
// used for HSA packets that enforce synchronization with barrier bit
bool barrierBit;
QueueContext(HSAQueueDescriptor* q_desc,
AQLRingBuffer* aql_buf)
: qDesc(q_desc), aqlBuf(aql_buf), barrierBit(false)
QCntxt(HSAQueueDescriptor* q_desc, AQLRingBuffer* aql_buf) :
qDesc(q_desc), aqlBuf(aql_buf), barrierBit(false)
{}
QueueContext() : qDesc(NULL), aqlBuf(NULL), barrierBit(false) {}
} QCntxt;
QCntxt() : qDesc(NULL), aqlBuf(NULL), barrierBit(false) {}
};
class HSAPacketProcessor: public DmaDevice
{

16
src/dev/hsa/hsa_queue.hh
View File

@@ -39,18 +39,18 @@
namespace gem5
{
typedef enum
enum _hsa_queue_type_t
{
_HSA_QUEUE_TYPE_MULTI = 0,
_HSA_QUEUE_TYPE_SINGLE = 1
} _hsa_queue_type_t;
};
typedef struct _hsa_signal_s
struct _hsa_signal_t
{
uint64_t handle;
} _hsa_signal_t;
};
typedef struct _hsa_queue_s
struct _hsa_queue_t
{
_hsa_queue_type_t type;
uint32_t features;
@@ -59,11 +59,11 @@ typedef struct _hsa_queue_s
uint32_t size;
uint32_t reserved1;
uint64_t id;
} _hsa_queue_t;
};
typedef uint32_t _amd_queue_properties32_t;
typedef struct _amd_queue_s
struct _amd_queue_t
{
_hsa_queue_t hsa_queue;
uint32_t reserved1[4];
@@ -88,7 +88,7 @@ typedef struct _amd_queue_s
uint32_t reserved3[2];
_hsa_signal_t queue_inactive_signal;
uint32_t reserved4[14];
} _amd_queue_t;
};
} // namespace gem5

24
src/dev/storage/ide_disk.hh
View File

@@ -69,12 +69,12 @@ class ChunkGenerator;
#define PRD_COUNT_MASK 0xfffe
#define PRD_EOT_MASK 0x8000
typedef struct PrdEntry
struct PrdEntry_t
{
uint32_t baseAddr;
uint16_t byteCount;
uint16_t endOfTable;
} PrdEntry_t;
};
class PrdTableEntry
{
@@ -126,7 +126,7 @@ class PrdTableEntry
#define DEV0 (0)
#define DEV1 (1)
typedef struct CommandReg
struct CommandReg_t
{
uint16_t data;
uint8_t error;
@@ -140,9 +140,9 @@ typedef struct CommandReg
uint8_t head;
};
uint8_t command;
} CommandReg_t;
};
typedef enum Events
enum Events_t
{
None = 0,
Transfer,
@@ -151,9 +151,9 @@ typedef enum Events
PrdRead,
DmaRead,
DmaWrite
} Events_t;
};
typedef enum DevAction
enum DevAction_t
{
ACT_NONE = 0,
ACT_CMD_WRITE,
@@ -170,9 +170,9 @@ typedef enum DevAction
ACT_DMA_DONE,
ACT_SRST_SET,
ACT_SRST_CLEAR
} DevAction_t;
};
typedef enum DevState
enum DevState_t
{
// Device idle
Device_Idle_S = 0,
@@ -199,14 +199,14 @@ typedef enum DevState
Prepare_Data_Dma,
Transfer_Data_Dma,
Device_Dma_Abort
} DevState_t;
};
typedef enum DmaState
enum DmaState_t
{
Dma_Idle = 0,
Dma_Start,
Dma_Transfer
} DmaState_t;
};
class IdeController;