Move all of the parameters of the Root SimObject so they are

directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3

src/python/m5/objects/BaseCPU.py

@@ -47,8 +47,8 @@ class BaseCPU(SimObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    clock = Param.Clock(Parent.clock, "clock speed")
-    phase = Param.Latency("0ns", "clock phase")
+    clock = Param.Clock('1t', "clock speed")
+    phase = Param.Latency('0ns', "clock phase")
 
     _mem_ports = []
 

src/python/m5/objects/PhysicalMemory.py

@@ -8,7 +8,7 @@ class PhysicalMemory(MemObject):
     functional = Port("Functional Access Port")
     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
     file = Param.String('', "memory mapped file")
-    latency = Param.Latency(Parent.clock, "latency of an access")
+    latency = Param.Latency('1t', "latency of an access")
     zero = Param.Bool(False, "zero initialize memory")
 
 class DRAMMemory(PhysicalMemory):

src/python/m5/objects/Root.py

@@ -3,9 +3,4 @@ from m5.params import *
 
 class Root(SimObject):
     type = 'Root'
-    clock = Param.RootClock('1THz', "tick frequency")
-    max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
-    progress_interval = Param.Tick('0',
-        "print a progress message every n ticks (0 = never)")
-    output_file = Param.String('cout', "file to dump simulator output to")
-    checkpoint = Param.String('', "checkpoint file to load")
+    dummy = Param.Int(0, "We don't support objects without params")