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cpu: Eliminate the (read|set)VecPredReg helpers from ThreadContext.

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Change-Id: I9f220ba4f28d6a63e4f037388b0431dfe123a8a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49703
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-08-11 03:59:27 -07:00
parent 5c3a6a4e13
commit d53f75c1eb
2 changed files with 2 additions and 21 deletions
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4
src/cpu/thread_context.cc
View File

@@ -231,7 +231,7 @@ serialize(const ThreadContext &tc, CheckpointOut &cp)
const size_t numPreds = regClasses.at(VecPredRegClass).numRegs();
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
for (int i = 0; i < numPreds; ++i) {
vecPredRegs[i] = tc.readVecPredRegFlat(i);
tc.getRegFlat(RegId(VecPredRegClass, i), &vecPredRegs[i]);
}
SERIALIZE_CONTAINER(vecPredRegs);
@@ -278,7 +278,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
UNSERIALIZE_CONTAINER(vecPredRegs);
for (int i = 0; i < numPreds; ++i) {
tc.setVecPredRegFlat(i, vecPredRegs[i]);
tc.setRegFlat(RegId(VecPredRegClass, i), &vecPredRegs[i]);
}
const size_t numInts = regClasses.at(IntRegClass).numRegs();

19
src/cpu/thread_context.hh
View File

@@ -374,25 +374,6 @@ class ThreadContext : public PCEventScope
setRegFlat(RegId(VecElemClass, idx), val);
}
TheISA::VecPredRegContainer
readVecPredRegFlat(RegIndex idx) const
{
TheISA::VecPredRegContainer val;
getRegFlat(RegId(VecPredRegClass, idx), &val);
return val;
}
TheISA::VecPredRegContainer&
getWritableVecPredRegFlat(RegIndex idx)
{
return *(TheISA::VecPredRegContainer *)getWritableRegFlat(
RegId(VecPredRegClass, idx));
}
void
setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer& val)
{
setRegFlat(RegId(VecPredRegClass, idx), &val);
}
RegVal
readCCRegFlat(RegIndex idx) const
{