From d537ded9d225f04ebdcb2d64585f30c8e7f7756d Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 16 May 2023 15:42:00 +0100 Subject: [PATCH] arch-arm: Fix printing of VecElemClass registers At the moment it is not possible to trace the value of VecElemClass registers. If a AArch32 SIMD binary is run with tracing on, simulation will fail the following assertion [1]. std::string valString(const void *val, size_t size) const override { assert(size == sizeof(ValueType)); The problem is that Arm VecElems are stored in RegVal (uint64_t), but the VecElem data type (ValueType above) per se is a uint32_t. So valString is getting called with size = 8 (coming from RegVal) but ValueType has size = 4. We fix this problem by using RegVal as a VecElemRegClassOps template parameter to make them match. This is not changing anything from a functionality perspective. The result will be that we will be able to print VecElems as 64bit values. This solution is the most simple one but a bit dirty. I believe in the long term we should make the VecElemClass use the void* interface rather than the RegVal one. In this way we will be able to correctly print the VecElem size as 32bit value. [1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362 Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70697 Tested-by: kokoro Reviewed-by: Richard Cooper Maintainer: Jason Lowe-Power --- src/arch/arm/regs/vec.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh index 00ab87fbcb..19f37c916d 100644 --- a/src/arch/arm/regs/vec.hh +++ b/src/arch/arm/regs/vec.hh @@ -93,7 +93,7 @@ const int VECREG_UREG0 = 32; const int PREDREG_FFR = 16; const int PREDREG_UREG0 = 17; -static inline VecElemRegClassOps +static inline VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg); static inline TypedRegClassOps vecRegClassOps; static inline TypedRegClassOps vecPredRegClassOps;