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Merge branch 'develop' into develop-kconfig

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This commit is contained in:
Bobby R. Bruce
2023-11-27 09:39:08 -08:00
committed by GitHub
parent 92670e9745 0f6eabe8c9
commit d4b7c8a26d
18 changed files with 211 additions and 124 deletions
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2
src/arch/amdgpu/gcn3/insts/instructions.cc
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@@ -29692,7 +29692,7 @@ namespace Gcn3ISA
for (int i = 0; i < 4 ; ++i) {
VecElemU32 permuted_val = permute(selector, 0xFF
& ((VecElemU32)src2[lane] >> (8 * i)));
vdst[lane] |= (permuted_val << i);
vdst[lane] |= (permuted_val << (8 * i));
}
DPRINTF(GCN3, "v_perm result: 0x%08x\n", vdst[lane]);

2
src/arch/amdgpu/vega/decoder.cc
View File

@@ -7020,7 +7020,7 @@ namespace VegaISA
GPUStaticInst*
Decoder::decode_OPU_VOP3__V_OR3_B32(MachInst iFmt)
{
return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
return new Inst_VOP3__V_OR3_B32(&iFmt->iFmt_VOP3A);
}
GPUStaticInst*

2
src/arch/amdgpu/vega/insts/instructions.cc
View File

@@ -32671,7 +32671,7 @@ namespace VegaISA
for (int i = 0; i < 4 ; ++i) {
VecElemU32 permuted_val = permute(selector, 0xFF
& ((VecElemU32)src2[lane] >> (8 * i)));
vdst[lane] |= (permuted_val << i);
vdst[lane] |= (permuted_val << (8 * i));
}
DPRINTF(VEGA, "v_perm result: 0x%08x\n", vdst[lane]);

124
src/arch/arm/interrupts.cc
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@@ -285,4 +285,128 @@ ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
}
bool
ArmISA::Interrupts::takeVirtualInt(InterruptTypes int_type) const
{
return ArmSystem::highestELIs64(tc) ? takeVirtualInt64(int_type) :
takeVirtualInt32(int_type);
}
bool
ArmISA::Interrupts::takeVirtualInt32(InterruptTypes int_type) const
{
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE);
bool amo, fmo, imo;
bool cpsr_mask_bit, hcr_mask_override_bit;
if (hcr.tge == 1){
amo = (no_vhe || hcr.e2h == 0);
fmo = (no_vhe || hcr.e2h == 0);
imo = (no_vhe || hcr.e2h == 0);
} else {
amo = hcr.amo;
fmo = hcr.fmo;
imo = hcr.imo;
}
bool is_hyp_mode = currEL(tc) == EL2;
bool is_secure = ArmISA::isSecure(tc);
switch(int_type) {
case INT_VIRT_FIQ:
cpsr_mask_bit = cpsr.f;
hcr_mask_override_bit = fmo;
break;
case INT_VIRT_IRQ:
cpsr_mask_bit = cpsr.i;
hcr_mask_override_bit = imo;
break;
case INT_VIRT_ABT:
cpsr_mask_bit = cpsr.a;
hcr_mask_override_bit = amo;
break;
default:
panic("Unhandled interrupt type!");
}
return !cpsr_mask_bit && hcr_mask_override_bit &&
!is_secure && !is_hyp_mode;
}
bool
ArmISA::Interrupts::takeVirtualInt64(InterruptTypes int_type) const
{
InterruptMask mask;
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
ExceptionLevel el = currEL(tc);
bool cpsr_mask_bit, hcr_mask_override_bit;
bool is_secure = ArmISA::isSecureBelowEL3(tc);
switch(int_type) {
case INT_VIRT_FIQ:
cpsr_mask_bit = cpsr.f;
hcr_mask_override_bit = hcr.fmo;
break;
case INT_VIRT_IRQ:
cpsr_mask_bit = cpsr.i;
hcr_mask_override_bit = hcr.imo;
break;
case INT_VIRT_ABT:
cpsr_mask_bit = cpsr.a;
hcr_mask_override_bit = hcr.amo;
break;
default:
panic("Unhandled interrupt type!");
}
if (is_secure) {
if (!scr.eel2) {
// NS=0,EEL2=0
mask = INT_MASK_P;
} else {
if (!hcr.tge) {
if (!hcr_mask_override_bit) {
// NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=0
mask = INT_MASK_P;
} else {
// NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=1
if (el == EL2 || el == EL3)
mask = INT_MASK_P;
else
mask = INT_MASK_M;
}
} else {
// NS=0,EEL2=1,TGE=1
mask = INT_MASK_P;
}
}
} else {
if (!hcr.tge) {
if (!hcr_mask_override_bit) {
// NS=1,TGE=0,AMO/IMO/FMO=0
mask = INT_MASK_P;
} else {
// NS=1,TGE=0,AMO/IMO/FMO=1
if (el == EL2 || el == EL3)
mask = INT_MASK_P;
else
mask = INT_MASK_M;
}
} else {
// NS=1,TGE=1
mask = INT_MASK_P;
}
}
return ((mask == INT_MASK_T) ||
((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
(mask != INT_MASK_P);
}
} // namespace gem5

129
src/arch/arm/interrupts.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2016 ARM Limited
* Copyright (c) 2010, 2012-2013, 2016, 2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -65,7 +65,11 @@ enum InterruptTypes
INT_SEV, // Special interrupt for recieving SEV's
INT_VIRT_IRQ,
INT_VIRT_FIQ,
NumInterruptTypes
NumInterruptTypes,
// Cannot be raised by an external signal
// (for now) from the IC so we don't instantiate a
// interrupt entry in the state array
INT_VIRT_ABT
};
class Interrupts : public BaseInterrupts
@@ -132,6 +136,10 @@ class Interrupts : public BaseInterrupts
bool takeInt32(InterruptTypes int_type) const;
bool takeInt64(InterruptTypes int_type) const;
bool takeVirtualInt(InterruptTypes int_type) const;
bool takeVirtualInt32(InterruptTypes int_type) const;
bool takeVirtualInt64(InterruptTypes int_type) const;
bool
checkInterrupts() const override
{
@@ -140,41 +148,15 @@ class Interrupts : public BaseInterrupts
if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
return false;
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE);
bool amo, fmo, imo;
if (hcr.tge == 1){
amo = (no_vhe || hcr.e2h == 0);
fmo = (no_vhe || hcr.e2h == 0);
imo = (no_vhe || hcr.e2h == 0);
} else {
amo = hcr.amo;
fmo = hcr.fmo;
imo = hcr.imo;
}
bool isHypMode = currEL(tc) == EL2;
bool isSecure = ArmISA::isSecure(tc);
bool allowVIrq = !cpsr.i && imo && !isSecure && !isHypMode;
bool allowVFiq = !cpsr.f && fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && amo && !isSecure && !isHypMode;
if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
(hcr.va && allowVAbort)) )
return false;
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
return ((interrupts[INT_IRQ] && take_irq) ||
(interrupts[INT_FIQ] && take_fiq) ||
(interrupts[INT_ABT] && take_ea) ||
((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
(hcr.va && allowVAbort) ||
(interrupts[INT_RST]) ||
return ((interrupts[INT_IRQ] && takeInt(INT_IRQ)) ||
(interrupts[INT_FIQ] && takeInt(INT_FIQ)) ||
(interrupts[INT_ABT] && takeInt(INT_ABT)) ||
((interrupts[INT_VIRT_IRQ] || hcr.vi) &&
takeVirtualInt(INT_VIRT_IRQ)) ||
((interrupts[INT_VIRT_FIQ] || hcr.vf) &&
takeVirtualInt(INT_VIRT_FIQ)) ||
(hcr.va && takeVirtualInt(INT_VIRT_ABT)) ||
(interrupts[INT_RST]) ||
(interrupts[INT_SEV])
);
}
@@ -187,30 +169,29 @@ class Interrupts : public BaseInterrupts
bool
checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
{
uint64_t maskedIntStatus;
bool virtWake;
uint64_t masked_int_status;
bool virt_wake;
maskedIntStatus = intStatus & ~((1 << INT_VIRT_IRQ) |
(1 << INT_VIRT_FIQ));
virtWake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
virtWake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
virtWake |= hcr.va && hcr.amo;
virtWake &= (cpsr.mode != MODE_HYP) && !isSecure(tc);
return maskedIntStatus || virtWake;
masked_int_status = intStatus & ~((1 << INT_VIRT_IRQ) |
(1 << INT_VIRT_FIQ));
virt_wake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
virt_wake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
virt_wake |= hcr.va && hcr.amo;
virt_wake &= currEL(cpsr) < EL2 && EL2Enabled(tc);
return masked_int_status || virt_wake;
}
uint32_t
getISR(HCR hcr, CPSR cpsr, SCR scr)
{
bool useHcrMux;
CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
bool use_hcr_mux = currEL(cpsr) < EL2 && EL2Enabled(tc);
ISR isr = 0;
useHcrMux = (cpsr.mode != MODE_HYP) && !isSecure(tc);
isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
: interrupts[INT_IRQ];
isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
: interrupts[INT_FIQ];
isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
isr.i = (use_hcr_mux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
: interrupts[INT_IRQ];
isr.f = (use_hcr_mux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
: interrupts[INT_FIQ];
isr.a = (use_hcr_mux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
return isr;
}
@@ -239,44 +220,20 @@ class Interrupts : public BaseInterrupts
assert(checkInterrupts());
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE);
bool amo, fmo, imo;
if (hcr.tge == 1){
amo = (no_vhe || hcr.e2h == 0);
fmo = (no_vhe || hcr.e2h == 0);
imo = (no_vhe || hcr.e2h == 0);
} else {
amo = hcr.amo;
fmo = hcr.fmo;
imo = hcr.imo;
}
// Calculate a few temp vars so we can work out if there's a pending
// virtual interrupt, and if its allowed to happen
// ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
bool isHypMode = currEL(tc) == EL2;
bool isSecure = ArmISA::isSecure(tc);
bool allowVIrq = !cpsr.i && imo && !isSecure && !isHypMode;
bool allowVFiq = !cpsr.f && fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && amo && !isSecure && !isHypMode;
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
if (interrupts[INT_IRQ] && take_irq)
if (interrupts[INT_IRQ] && takeInt(INT_IRQ))
return std::make_shared<Interrupt>();
if ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq)
if ((interrupts[INT_VIRT_IRQ] || hcr.vi) &&
takeVirtualInt(INT_VIRT_IRQ))
return std::make_shared<VirtualInterrupt>();
if (interrupts[INT_FIQ] && take_fiq)
if (interrupts[INT_FIQ] && takeInt(INT_FIQ))
return std::make_shared<FastInterrupt>();
if ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq)
if ((interrupts[INT_VIRT_FIQ] || hcr.vf) &&
takeVirtualInt(INT_VIRT_FIQ))
return std::make_shared<VirtualFastInterrupt>();
if (interrupts[INT_ABT] && take_ea)
if (interrupts[INT_ABT] && takeInt(INT_ABT))
return std::make_shared<SystemError>();
if (hcr.va && allowVAbort)
if (hcr.va && takeVirtualInt(INT_VIRT_ABT))
return std::make_shared<VirtualDataAbort>(
0, TlbEntry::DomainType::NoAccess, false,
ArmFault::AsynchronousExternalAbort);

6
src/arch/arm/regs/misc_types.hh
View File

@@ -75,6 +75,12 @@ namespace ArmISA
Bitfield<0> sp; // AArch64
EndBitUnion(CPSR)
BitUnion32(ISR)
Bitfield<8> a;
Bitfield<7> i;
Bitfield<6> f;
EndBitUnion(ISR)
BitUnion32(ISAR5)
Bitfield<31, 28> vcma;
Bitfield<27, 24> rdm;

4
src/mem/cache/Cache.py vendored
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@@ -1,4 +1,4 @@
# Copyright (c) 2012-2013, 2015, 2018, 2022 Arm Limited
# Copyright (c) 2012-2013, 2015, 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -112,7 +112,7 @@ class BaseCache(ClockedObject):
"Notify the hardware prefetcher on every access (not just misses)",
)
prefetch_on_pf_hit = Param.Bool(
True, "Notify the hardware prefetcher on hit on prefetched lines"
False, "Notify the hardware prefetcher on hit on prefetched lines"
)
tags = Param.BaseTags(BaseSetAssoc(), "Tag store")

9
src/mem/cache/prefetch/Prefetcher.py vendored
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@@ -1,4 +1,4 @@
# Copyright (c) 2012, 2014, 2019, 2022 Arm Limited
# Copyright (c) 2012, 2014, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -192,13 +192,6 @@ class StridePrefetcher(QueuedPrefetcher):
use_requestor_id = Param.Bool(True, "Use requestor id based history")
degree = Param.Int(4, "Number of prefetches to generate")
distance = Param.Unsigned(
0,
"How far ahead of the demand stream to start prefetching. "
"Skip this number of strides ahead of the first identified prefetch, "
"then generate `degree` prefetches at `stride` intervals. "
"A value of zero indicates no skip.",
)
table_assoc = Param.Int(4, "Associativity of the PC table")
table_entries = Param.MemorySize("64", "Number of entries of the PC table")

3
src/mem/cache/prefetch/base.cc vendored
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, 2022 Arm Limited
* Copyright (c) 2013-2014 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -245,7 +245,6 @@ Base::probeNotify(const PacketPtr &pkt, bool miss)
// operations or for writes that we are coaslescing.
if (pkt->cmd.isSWPrefetch()) return;
if (pkt->req->isCacheMaintenance()) return;
if (pkt->isCleanEviction()) return;
if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
if (!pkt->req->hasPaddr()) {
panic("Request must have a physical address");

4
src/mem/cache/prefetch/queued.cc vendored
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2015, 2022 Arm Limited
* Copyright (c) 2014-2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -178,7 +178,7 @@ Queued::notify(const PacketPtr &pkt, const PrefetchInfo &pfi)
if (queueSquash) {
auto itr = pfq.begin();
while (itr != pfq.end()) {
if (blockAddress(itr->pfInfo.getAddr()) == blk_addr &&
if (itr->pfInfo.getAddr() == blk_addr &&
itr->pfInfo.isSecure() == is_secure) {
DPRINTF(HWPrefetch, "Removing pf candidate addr: %#x "
"(cl: %#x), demand request going to the same addr\n",

19
src/mem/cache/prefetch/stride.cc vendored
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 Inria
* Copyright (c) 2012-2013, 2015, 2022-2023 Arm Limited
* Copyright (c) 2012-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -84,7 +84,6 @@ Stride::Stride(const StridePrefetcherParams &p)
threshConf(p.confidence_threshold/100.0),
useRequestorId(p.use_requestor_id),
degree(p.degree),
distance(p.distance),
pcTableInfo(p.table_assoc, p.table_entries, p.table_indexing_policy,
p.table_replacement_policy)
{
@@ -168,16 +167,16 @@ Stride::calculatePrefetch(const PrefetchInfo &pfi,
return;
}
// Round strides up to atleast 1 cacheline
int prefetch_stride = new_stride;
if (abs(new_stride) < blkSize) {
prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
}
Addr new_addr = pf_addr + distance * prefetch_stride;
// Generate up to degree prefetches
for (int d = 1; d <= degree; d++) {
addresses.push_back(AddrPriority(new_addr += prefetch_stride, 0));
// Round strides up to atleast 1 cacheline
int prefetch_stride = new_stride;
if (abs(new_stride) < blkSize) {
prefetch_stride = (new_stride < 0) ? -blkSize : blkSize;
}
Addr new_addr = pf_addr + d * prefetch_stride;
addresses.push_back(AddrPriority(new_addr, 0));
}
} else {
// Miss in table

4
src/mem/cache/prefetch/stride.hh vendored
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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018 Inria
* Copyright (c) 2012-2013, 2015, 2022 Arm Limited
* Copyright (c) 2012-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -105,8 +105,6 @@ class Stride : public Queued
const int degree;
const int distance;
/**
* Information used to create a new PC table. All of them behave equally.
*/