diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 07123bd7dc..ebe72dd52e 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1228,6 +1228,11 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
                 break;
             }
             break;
+          case 11:
+          case 15:
+            // SYS Instruction with CRn = { 11, 15 }
+            // (Trappable by HCR_EL2.TIDCP)
+            return MISCREG_IMPDEF_UNIMPL;
         }
         break;
       case 2: