Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.

src/cpu/o3/commit_impl.hh:
    Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
    Deallocate and activate threads properly.  Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
    Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
    Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
    More debug output.
src/cpu/o3/lsq_unit_impl.hh:
    Fixup store conditional handling (still a bit of a hack, but works now).

    Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
    Deallocate context now records if the context should be fully removed.

--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9

src/cpu/o3/commit_impl.hh

@@ -342,12 +342,6 @@ DefaultCommit<Impl>::drain()
 {
     drainPending = true;
 
-    // If it's already drained, return true.
-    if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
-        cpu->signalDrained();
-        return true;
-    }
-
     return false;
 }
 
@@ -1218,16 +1212,16 @@ DefaultCommit<Impl>::skidInsert()
 
     for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
         DynInstPtr inst = fromRename->insts[inst_num];
-        int tid = inst->threadNumber;
 
         if (!inst->isSquashed()) {
             DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
-                    "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+                    "skidBuffer.\n", inst->readPC(), inst->seqNum,
+                    inst->threadNumber);
             skidBuffer.push(inst);
         } else {
             DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                     "squashed, skipping.\n",
-                    inst->readPC(), inst->seqNum, tid);
+                    inst->readPC(), inst->seqNum, inst->threadNumber);
         }
     }
 }