From d454e421d231246a443231c7d94e0761feabf0ec Mon Sep 17 00:00:00 2001
From: "Bobby R. Bruce" <bbruce@ucdavis.edu>
Date: Thu, 17 Oct 2024 10:29:17 -0700
Subject: [PATCH] stdlib,arch-x86: Update X86Demoboard (#1618)

This commit modifies X86DemoBoard so it has numbers more similar to that
of RiscvDemoBoard and ArmDemoBoard. It also adds SE mode to
X86DemoBoard. Note that the changes here depend on the changes in PR
1579.

**Note**: This PR was created so @BobbyRBruce could add his commits to
#1600

---------

Co-authored-by: Erin Le <ejle@ucdavis.edu>
---
 .../gem5/prebuilt/demo/x86_demo_board.py      | 85 ++++++++++++++-----
 1 file changed, 65 insertions(+), 20 deletions(-)

diff --git a/src/python/gem5/prebuilt/demo/x86_demo_board.py b/src/python/gem5/prebuilt/demo/x86_demo_board.py
index 793b43a3d1..ac89847f2b 100644
--- a/src/python/gem5/prebuilt/demo/x86_demo_board.py
+++ b/src/python/gem5/prebuilt/demo/x86_demo_board.py
@@ -24,27 +24,33 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    IOXBar,
+    Pc,
+    Port,
+    X86FsLinux,
+)
 from m5.util import warn
 
-from ...coherence_protocol import CoherenceProtocol
+from ...components.boards.se_binary_workload import SEBinaryWorkload
 from ...components.boards.x86_board import X86Board
-from ...components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
-    MESITwoLevelCacheHierarchy,
+from ...components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import (
+    PrivateL1SharedL2CacheHierarchy,
 )
-from ...components.memory.single_channel import SingleChannelDDR3_1600
+from ...components.memory.multi_channel import DualChannelDDR4_2400
 from ...components.processors.cpu_types import CPUTypes
 from ...components.processors.simple_processor import SimpleProcessor
 from ...isas import ISA
+from ...utils.override import overrides
 from ...utils.requires import requires
 
 
-class X86DemoBoard(X86Board):
+class X86DemoBoard(X86Board, SEBinaryWorkload):
     """
     This prebuilt X86 board is used for demonstration purposes. It simulates
-    an X86 3GHz quad-core system with a 2GiB DDR3_1600 memory system. A
-    MESI_Two_Level cache hierarchy is set with an l1 data and instruction
-    cache, each 32KiB with an associativity of 8, and a single bank l2 cache of
-    1MiB with an associativity of 16.
+    an X86 3GHz dual-core system with a 3GiB DDR4_2400 memory system. The
+    cache hierarchy consists of per-core private L1 instruction and data
+    caches (64KiB each) connected to a shared 8MiB L2 cache.
 
     **DISCLAIMER**: This board is solely for demonstration purposes. This board
     is not known to be representative of any real-world system or produce
@@ -68,7 +74,6 @@ class X86DemoBoard(X86Board):
     def __init__(self):
         requires(
             isa_required=ISA.X86,
-            coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
         )
 
         warn(
@@ -77,18 +82,15 @@ class X86DemoBoard(X86Board):
             "real-world system. Use with caution."
         )
 
-        memory = SingleChannelDDR3_1600(size="2GiB")
+        # The other demo boards have 4 GiB of memory, but X86Board can only
+        # support up to 3 GiB.
+        memory = DualChannelDDR4_2400(size="3GiB")
         processor = SimpleProcessor(
-            cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4
+            cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=2
         )
-        cache_hierarchy = MESITwoLevelCacheHierarchy(
-            l1d_size="32KiB",
-            l1d_assoc=8,
-            l1i_size="32KiB",
-            l1i_assoc=8,
-            l2_size="1MiB",
-            l2_assoc=16,
-            num_l2_banks=1,
+
+        cache_hierarchy = PrivateL1SharedL2CacheHierarchy(
+            l1d_size="64KiB", l1i_size="64KiB", l2_size="8MiB"
         )
 
         super().__init__(
@@ -97,3 +99,46 @@ class X86DemoBoard(X86Board):
             memory=memory,
             cache_hierarchy=cache_hierarchy,
         )
+
+    @overrides(X86Board)
+    def _setup_board(self) -> None:
+        if self._is_fs:
+            self.pc = Pc()
+
+            self.workload = X86FsLinux()
+
+            # North Bridge
+            self.iobus = IOXBar()
+
+            # Set up all of the I/O.
+            self._setup_io_devices()
+
+            self.m5ops_base = 0xFFFF0000
+
+    @overrides(X86Board)
+    def has_io_bus(self) -> bool:
+        return self.is_fullsystem()
+
+    @overrides(X86Board)
+    def get_io_bus(self) -> IOXBar:
+        if self.has_io_bus():
+            return self.iobus
+        else:
+            raise NotImplementedError(
+                "X86DemoBoard does not have an IO bus. "
+                "Use `has_io_bus()` to check this."
+            )
+
+    @overrides(X86Board)
+    def has_coherent_io(self) -> bool:
+        return self.is_fullsystem()
+
+    @overrides(X86Board)
+    def get_mem_side_coherent_io_port(self) -> Port:
+        if self.has_coherent_io():
+            return self.iobus.mem_side_ports
+        else:
+            raise NotImplementedError(
+                "x86DemoBoard does not have any I/O ports. Use has_coherent_io"
+                " to check this."
+            )