diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index b612516fcc..2196ee51cd 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1067,8 +1067,8 @@ AbortFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) tc->setMiscReg(T::FsrIndex, fsr); tc->setMiscReg(T::FarIndex, faultAddr); } - DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ - "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); + DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x\n", + source, fsr, faultAddr); } else { // AArch64 // Set the FAR register. Nothing else to do if we are in AArch64 state // because the syndrome register has already been set inside invoke64() @@ -1092,11 +1092,11 @@ template void AbortFault::update(ThreadContext *tc) { - if (tranMethod == ArmFault::UnknownTran) { - tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran - : ArmFault::VmsaTran; + if (tranMethod == TranMethod::UnknownTran) { + tranMethod = longDescFormatInUse(tc) ? TranMethod::LpaeTran + : TranMethod::VmsaTran; - if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { + if ((tranMethod == TranMethod::VmsaTran) && this->routeToMonitor(tc)) { // See ARM ARM B3-1416 bool override_LPAE = false; TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); @@ -1109,7 +1109,7 @@ AbortFault::update(ThreadContext *tc) "override detected.\n"); } if (override_LPAE) - tranMethod = ArmFault::LpaeTran; + tranMethod = TranMethod::LpaeTran; } } @@ -1139,8 +1139,8 @@ AbortFault::getFaultStatusCode(ThreadContext *tc) const if (!this->to64) { // AArch32 - assert(tranMethod != ArmFault::UnknownTran); - if (tranMethod == ArmFault::LpaeTran) { + assert(tranMethod != TranMethod::UnknownTran); + if (tranMethod == TranMethod::LpaeTran) { fsc = ArmFault::longDescFaultSources[source]; } else { fsc = ArmFault::shortDescFaultSources[source]; @@ -1162,8 +1162,8 @@ AbortFault::getFsr(ThreadContext *tc) const auto fsc = getFaultStatusCode(tc); // AArch32 - assert(tranMethod != ArmFault::UnknownTran); - if (tranMethod == ArmFault::LpaeTran) { + assert(tranMethod != TranMethod::UnknownTran); + if (tranMethod == TranMethod::LpaeTran) { fsr.status = fsc; fsr.lpae = 1; } else { diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index a76439574a..fb6ba37122 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -147,13 +147,6 @@ class ArmFault : public FaultBase AR // DataAbort: Acquire/Release semantics }; - enum TranMethod - { - LpaeTran, - VmsaTran, - UnknownTran - }; - enum DebugType { NODEBUG = 0, @@ -485,13 +478,13 @@ class AbortFault : public ArmFaultVals uint8_t srcEncoded; bool stage2; bool s1ptw; - ArmFault::TranMethod tranMethod; + TranMethod tranMethod; ArmFault::DebugType debugType; public: AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, bool _stage2, - ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran, + TranMethod _tranMethod = TranMethod::UnknownTran, ArmFault::DebugType _debug = ArmFault::NODEBUG) : faultAddr(_faultAddr), OVAddr(0), write(_write), domain(_domain), source(_source), srcEncoded(0), @@ -523,10 +516,10 @@ class PrefetchAbort : public AbortFault static const MiscRegIndex HFarIndex = MISCREG_HIFAR; PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, - ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran, + TranMethod _tran_method = TranMethod::UnknownTran, ArmFault::DebugType _debug = ArmFault::NODEBUG) : AbortFault(_addr, false, TlbEntry::DomainType::NoAccess, - _source, _stage2, _tranMethod, _debug) + _source, _stage2, _tran_method, _debug) {} // @todo: external aborts should be routed if SCR.EA == 1 @@ -558,10 +551,10 @@ class DataAbort : public AbortFault DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, bool _stage2=false, - ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, + TranMethod _tran_method=TranMethod::UnknownTran, ArmFault::DebugType _debug_type=ArmFault::NODEBUG) : AbortFault(_addr, _write, _domain, _source, _stage2, - _tranMethod, _debug_type), + _tran_method, _debug_type), isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false) {} diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 34155f0f0d..ca78586dd8 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -646,7 +646,7 @@ ArmStaticInst::softwareBreakpoint32(ExecContext *xc, uint16_t imm) const return std::make_shared(readPC(xc), ArmFault::DebugEvent, false, - ArmFault::UnknownTran, + TranMethod::UnknownTran, ArmFault::BRKPOINT); } } diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc index 0381176b3f..24366597e2 100644 --- a/src/arch/arm/mmu.cc +++ b/src/arch/arm/mmu.cc @@ -279,7 +279,7 @@ MMU::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, vaddr_tainted, TlbEntry::DomainType::NoAccess, is_write, ArmFault::AlignmentFault, state.isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); } } } @@ -321,8 +321,8 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, bool is_priv = state.isPriv && !(flags & UserMode); // Get the translation type from the actuall table entry - ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran - : ArmFault::VmsaTran; + TranMethod tran_method = te->longDescFormat ? + TranMethod::LpaeTran : TranMethod::VmsaTran; // If this is the second stage of translation and the request is for a // stage 1 page table walk then we need to check the HCR.PTW bit. This @@ -333,7 +333,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( vaddr, te->domain, is_write, ArmFault::PermissionLL + te->lookupLevel, - state.isStage2, tranMethod); + state.isStage2, tran_method); } // Generate an alignment fault for unaligned data accesses to device or @@ -345,7 +345,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( vaddr, TlbEntry::DomainType::NoAccess, is_write, ArmFault::AlignmentFault, state.isStage2, - tranMethod); + tran_method); } } } @@ -357,7 +357,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, // desc. format in all cases return std::make_shared( vaddr, ArmFault::PrefetchUncacheable, - state.isStage2, tranMethod); + state.isStage2, tran_method); } } @@ -375,12 +375,12 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( req->getPC(), ArmFault::DomainLL + te->lookupLevel, - state.isStage2, tranMethod); + state.isStage2, tran_method); } else return std::make_shared( vaddr, te->domain, is_write, ArmFault::DomainLL + te->lookupLevel, - state.isStage2, tranMethod); + state.isStage2, tran_method); case 1: // Continue with permissions check break; @@ -471,7 +471,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( req->getPC(), ArmFault::PermissionLL + te->lookupLevel, - state.isStage2, tranMethod); + state.isStage2, tran_method); } else if (abt | hapAbt) { stats.permsFaults++; DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" @@ -479,7 +479,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( vaddr, te->domain, is_write, ArmFault::PermissionLL + te->lookupLevel, - state.isStage2 | !abt, tranMethod); + state.isStage2 | !abt, tran_method); } return NoFault; } @@ -527,7 +527,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( vaddr_tainted, te->domain, is_write, ArmFault::PermissionLL + te->lookupLevel, - state.isStage2, ArmFault::LpaeTran); + state.isStage2, TranMethod::LpaeTran); } // Generate an alignment fault for unaligned accesses to device or @@ -541,7 +541,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, TlbEntry::DomainType::NoAccess, is_atomic ? false : is_write, ArmFault::AlignmentFault, state.isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } } } @@ -554,7 +554,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( vaddr_tainted, ArmFault::PrefetchUncacheable, - state.isStage2, ArmFault::LpaeTran); + state.isStage2, TranMethod::LpaeTran); } } @@ -584,7 +584,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, return std::make_shared( req->getPC(), ArmFault::PermissionLL + te->lookupLevel, - state.isStage2, ArmFault::LpaeTran); + state.isStage2, TranMethod::LpaeTran); } else { stats.permsFaults++; DPRINTF(TLB, "TLB Fault: Data abort on permission check." @@ -593,7 +593,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, vaddr_tainted, te->domain, (is_atomic && !grant_read) ? false : is_write, ArmFault::PermissionLL + te->lookupLevel, - state.isStage2, ArmFault::LpaeTran); + state.isStage2, TranMethod::LpaeTran); } } @@ -828,13 +828,13 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode, if (is_fetch) f = std::make_shared(vaddr, ArmFault::AddressSizeLL, state.isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); else f = std::make_shared( vaddr, TlbEntry::DomainType::NoAccess, is_atomic ? false : mode==Write, ArmFault::AddressSizeLL, state.isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); return f; } } @@ -883,7 +883,7 @@ Fault MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, - ArmFault::TranMethod tranMethod, CachedState &state) + TranMethod tran_method, CachedState &state) { TlbEntry *te = NULL; bool is_fetch = (mode == Execute); @@ -936,7 +936,7 @@ MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode, vaddr_tainted, TlbEntry::DomainType::NoAccess, is_write, ArmFault::AlignmentFault, state.isStage2, - tranMethod); + tran_method); } if (fault == NoFault) @@ -968,8 +968,8 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, bool is_fetch = (mode == Execute); bool is_write = (mode == Write); bool long_desc_format = state.aarch64 || longDescFormatInUse(tc); - ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran - : ArmFault::VmsaTran; + TranMethod tran_method = long_desc_format ? + TranMethod::LpaeTran : TranMethod::VmsaTran; DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", @@ -998,7 +998,7 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, vaddr_tainted, TlbEntry::DomainType::NoAccess, is_write, ArmFault::AlignmentFault, state.isStage2, - tranMethod); + tran_method); } } } @@ -1020,7 +1020,7 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, state.isStage2 ? "IPA" : "VA", vaddr_tainted, state.asid); // Translation enabled fault = translateMmuOn(tc, req, mode, translation, delay, timing, - functional, vaddr, tranMethod, state); + functional, vaddr, tran_method, state); } // Check for Debug Exceptions diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index 46d904278a..abe71a40b1 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh @@ -46,6 +46,7 @@ #include "arch/arm/utility.hh" #include "arch/generic/mmu.hh" #include "base/memoizer.hh" +#include "base/statistics.hh" #include "enums/ArmLookupLevel.hh" #include "params/ArmMMU.hh" @@ -270,7 +271,7 @@ class MMU : public BaseMMU CachedState &state); Fault translateMmuOn(ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, - Addr vaddr, ArmFault::TranMethod tranMethod, + Addr vaddr, TranMethod tran_method, CachedState &state); Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc index a99cf0a81e..3607b08a12 100644 --- a/src/arch/arm/self_debug.cc +++ b/src/arch/arm/self_debug.cc @@ -110,7 +110,7 @@ SelfDebug::triggerException(ThreadContext *tc, Addr vaddr) if (to32) { return std::make_shared(vaddr, ArmFault::DebugEvent, false, - ArmFault::UnknownTran, + TranMethod::UnknownTran, ArmFault::BRKPOINT); } else { return std::make_shared(vaddr, 0x22); @@ -147,7 +147,7 @@ SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr, return std::make_shared(vaddr, TlbEntry::DomainType::NoAccess, write, ArmFault::DebugEvent, cm, - ArmFault::UnknownTran, d); + TranMethod::UnknownTran, d); } else { return std::make_shared(0, vaddr, write, cm); } diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 4357b0057c..fa5ea6d463 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -640,14 +640,14 @@ TableWalker::processWalk() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); else return std::make_shared( currState->vaddr_tainted, TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( MISCREG_TTBR0, currState->tc, @@ -661,14 +661,14 @@ TableWalker::processWalk() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); else return std::make_shared( currState->vaddr_tainted, TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); } ttbr = ttbr1; currState->ttbcr.n = 0; @@ -758,7 +758,7 @@ TableWalker::processWalkLPAE() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); else return std::make_shared( currState->vaddr_tainted, @@ -766,7 +766,7 @@ TableWalker::processWalkLPAE() is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( MISCREG_TTBR0, currState->tc, @@ -784,7 +784,7 @@ TableWalker::processWalkLPAE() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); else return std::make_shared( currState->vaddr_tainted, @@ -792,7 +792,7 @@ TableWalker::processWalkLPAE() is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( MISCREG_TTBR1, currState->tc, @@ -809,14 +809,14 @@ TableWalker::processWalkLPAE() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); else return std::make_shared( currState->vaddr_tainted, TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, - isStage2, ArmFault::LpaeTran); + isStage2, TranMethod::LpaeTran); } } @@ -1074,14 +1074,14 @@ TableWalker::processWalkAArch64() return std::make_shared( currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L0, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } else { return std::make_shared( currState->vaddr_tainted, TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L0, - isStage2, ArmFault::LpaeTran); + isStage2, TranMethod::LpaeTran); } } @@ -1111,7 +1111,7 @@ TableWalker::processWalkAArch64() currState->vaddr_tainted, ArmFault::AddressSizeLL + start_lookup_level, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); else return std::make_shared( currState->vaddr_tainted, @@ -1119,7 +1119,7 @@ TableWalker::processWalkAArch64() is_atomic ? false : currState->isWrite, ArmFault::AddressSizeLL + start_lookup_level, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } Request::Flags flag = Request::PT_WALK; @@ -1687,7 +1687,7 @@ TableWalker::doL1Descriptor() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); else currState->fault = std::make_shared( @@ -1695,7 +1695,7 @@ TableWalker::doL1Descriptor() TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); return; case L1Descriptor::Section: if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) { @@ -1710,7 +1710,7 @@ TableWalker::doL1Descriptor() is_atomic ? false : currState->isWrite, ArmFault::AccessFlagLL + LookupLevel::L1, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); } if (currState->l1Desc.supersection()) { panic("Haven't implemented supersections\n"); @@ -1758,7 +1758,7 @@ TableWalker::generateLongDescFault(ArmFault::FaultSource src) currState->vaddr_tainted, src + currState->longDesc.lookupLevel, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } else { return std::make_shared( currState->vaddr_tainted, @@ -1766,7 +1766,7 @@ TableWalker::generateLongDescFault(ArmFault::FaultSource src) currState->req->isAtomic() ? false : currState->isWrite, src + currState->longDesc.lookupLevel, isStage2, - ArmFault::LpaeTran); + TranMethod::LpaeTran); } } @@ -1953,14 +1953,14 @@ TableWalker::doL2Descriptor() currState->vaddr_tainted, ArmFault::TranslationLL + LookupLevel::L2, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); else currState->fault = std::make_shared( currState->vaddr_tainted, currState->l1Desc.domain(), is_atomic ? false : currState->isWrite, ArmFault::TranslationLL + LookupLevel::L2, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); return; } @@ -1976,7 +1976,7 @@ TableWalker::doL2Descriptor() TlbEntry::DomainType::NoAccess, is_atomic ? false : currState->isWrite, ArmFault::AccessFlagLL + LookupLevel::L2, isStage2, - ArmFault::VmsaTran); + TranMethod::VmsaTran); } insertTableEntry(currState->l2Desc, false); diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index d0a578a524..e6b371ffb2 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -282,6 +282,13 @@ namespace ArmISA Secure }; + enum class TranMethod + { + LpaeTran, + VmsaTran, + UnknownTran + }; + enum ExceptionLevel { EL0 = 0,