ruby: replaces Time with Cycles in many places

The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.

src/mem/slicc/ast/EnqueueStatementAST.py

@@ -53,8 +53,8 @@ class EnqueueStatementAST(StatementAST):
         self.symtab.newSymbol(v)
 
         # Declare message
-        code("${{msg_type.ident}} *out_msg = \
-                new ${{msg_type.ident}}(curCycle());")
+        code("${{msg_type.ident}} *out_msg = "\
+             "new ${{msg_type.ident}}(curCycle());")
 
         # The other statements
         t = self.statements.generate(code, None)
@@ -67,7 +67,7 @@ class EnqueueStatementAST(StatementAST):
             try:
                 # see if this is an integer
                 latency = int(latency)
-                args.append("%s" % latency)
+                args.append("Cycles(%s)" % latency)
             except ValueError:
                 # if not, it should be a member
                 args.append("m_%s" % latency)

src/mem/slicc/ast/FuncCallExprAST.py

@@ -142,7 +142,7 @@ class FuncCallExprAST(ExprAST):
     }
 
     if (result == TransitionResult_ResourceStall) {
-        scheduleEvent(1);
+        scheduleEvent(Cycles(1));
 
         // Cannot do anything with this transition, go check next doable transition (mostly likely of next port)
     }
@@ -173,7 +173,7 @@ class FuncCallExprAST(ExprAST):
     }
 
     if (result1 == TransitionResult_ResourceStall) {
-        scheduleEvent(1);
+        scheduleEvent(Cycles(1));
         // Cannot do anything with this transition, go check next
         // doable transition (mostly likely of next port)
     }

src/mem/slicc/ast/InfixOperatorExprAST.py

@@ -47,7 +47,7 @@ class InfixOperatorExprAST(ExprAST):
         rtype = self.right.generate(rcode)
 
         # Figure out what the input and output types should be
-        if self.op in ("==", "!="):
+        if self.op in ("==", "!=", ">=", "<=", ">", "<"):
             output = "bool"
             if (ltype != rtype):
                 self.error("Type mismatch: left and right operands of " +
@@ -55,30 +55,35 @@ class InfixOperatorExprAST(ExprAST):
                            "left: '%s', right: '%s'",
                            self.op, ltype, rtype)
         else:
+            expected_types = []
+            output = None
+
             if self.op in ("&&", "||"):
                 # boolean inputs and output
-                inputs = "bool"
-                output = "bool"
-            elif self.op in ("==", "!=", ">=", "<=", ">", "<"):
-                # Integer inputs, boolean output
-                inputs = "int"
-                output = "bool"
+                expected_types = [("bool", "bool", "bool")]
+            elif self.op in ("<<", ">>"):
+                expected_types = [("int", "int", "int"),
+                                  ("Cycles", "int", "Cycles")]
+            elif self.op in ("+", "-", "*", "/"):
+                expected_types = [("int", "int", "int"),
+                                  ("Time", "Time", "Time"),
+                                  ("Cycles", "Cycles", "Cycles"),
+                                  ("Cycles", "int", "Cycles"),
+                                  ("int", "Cycles", "Cycles")]
             else:
-                # integer inputs and output
-                inputs = "int"
-                output = "int"
+                self.error("No operator matched with {0}!" .format(self.op))
 
-            inputs_type = self.symtab.find(inputs, Type)
+            for expected_type in expected_types:
+                left_input_type = self.symtab.find(expected_type[0], Type)
+                right_input_type = self.symtab.find(expected_type[1], Type)
 
-            if inputs_type != ltype:
-                self.left.error("Type mismatch: left operand of operator " +
-                                "'%s' expects type '%s', actual was '%s'",
-                                self.op, inputs, ltype)
+                if (left_input_type == ltype) and (right_input_type == rtype):
+                    output = expected_type[2]
 
-            if inputs_type != rtype:
-                self.right.error("Type mismatch: right operand of operator " +
-                                 "'%s' expects type '%s', actual was '%s'",
-                                 self.op, inputs, rtype)
+            if output == None:
+                self.error("Type mismatch: operands ({0}, {1}) for operator " \
+                           "'{2}' failed to match with the expected types" .
+                           format(ltype, rtype, self.op))
 
         # All is well
         fix = code.nofix()

src/mem/slicc/symbols/StateMachine.py

@@ -32,7 +32,8 @@ from slicc.symbols.Var import Var
 import slicc.generate.html as html
 import re
 
-python_class_map = {"int": "Int",
+python_class_map = {
+                    "int": "Int",
                     "uint32_t" : "UInt32",
                     "std::string": "String",
                     "bool": "Bool",
@@ -42,8 +43,9 @@ python_class_map = {"int": "Int",
                     "DirectoryMemory": "RubyDirectoryMemory",
                     "MemoryControl": "MemoryControl",
                     "DMASequencer": "DMASequencer",
-                    "Prefetcher":"Prefetcher"
-                    }
+                    "Prefetcher":"Prefetcher",
+                    "Cycles":"Cycles",
+                   }
 
 class StateMachine(Symbol):
     def __init__(self, symtab, ident, location, pairs, config_parameters):
@@ -629,7 +631,8 @@ $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{v
 
             if vtype.isBuffer:
                 if "recycle_latency" in var:
-                    code('$vid->setRecycleLatency(${{var["recycle_latency"]}});')
+                    code('$vid->setRecycleLatency( ' \
+                         'Cycles(${{var["recycle_latency"]}}));')
                 else:
                     code('$vid->setRecycleLatency(m_recycle_latency);')
 
@@ -1055,7 +1058,7 @@ ${ident}_Controller::wakeup()
             m_fully_busy_cycles++;
 
             // Wakeup in another cycle and try again
-            scheduleEvent(1);
+            scheduleEvent(Cycles(1));
             break;
         }
 ''')

src/mem/slicc/symbols/Type.py

@@ -423,6 +423,8 @@ operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
 #include <iostream>
 
 #include "mem/protocol/${{self.c_ident}}.hh"
+#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/system/System.hh"
 
 using namespace std;
 ''')