ruby: replaces Time with Cycles in many places

The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.

src/mem/ruby/slicc_interface/AbstractCacheEntry.hh

@@ -52,8 +52,6 @@ class AbstractCacheEntry : public AbstractEntry
     void changePermission(AccessPermission new_perm);
 
     Address m_Address; // Address of this block, required by CacheMemory
-    Time m_LastRef; // Last time this block was referenced, required
-                    // by CacheMemory
     int m_locked; // Holds info whether the address is locked,
                   // required for implementing LL/SC
 };

src/mem/ruby/slicc_interface/AbstractController.hh

@@ -106,7 +106,7 @@ class AbstractController : public ClockedObject, public Consumer
   protected:
     int m_transitions_per_cycle;
     int m_buffer_size;
-    int m_recycle_latency;
+    Cycles m_recycle_latency;
     std::string m_name;
     NodeID m_version;
     Network* m_net_ptr;

src/mem/ruby/slicc_interface/Controller.py

@@ -40,6 +40,6 @@ class RubyController(ClockedObject):
     transitions_per_cycle = \
         Param.Int(32, "no. of  SLICC state machine transitions per cycle")
     buffer_size = Param.Int(0, "max buffer size 0 means infinite")
-    recycle_latency = Param.Int(10, "")
+    recycle_latency = Param.Cycles(10, "")
     number_of_TBEs = Param.Int(256, "")
     ruby_system = Param.RubySystem("");

src/mem/ruby/slicc_interface/RubySlicc_Util.hh

@@ -37,9 +37,8 @@
 
 #include "debug/RubySlicc.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
-#include "mem/ruby/system/System.hh"
+#include "mem/packet.hh"
 
 inline int
 random(int n)
@@ -53,6 +52,8 @@ zero_time()
     return 0;
 }
 
+inline Cycles TimeToCycles(Time t) { return Cycles(t); }
+
 inline NodeID
 intToID(int nodenum)
 {