From d358813a7a5dd2872b80bc71a752d30f5888ce22 Mon Sep 17 00:00:00 2001
From: Robert Hauser <robert.hauser@uni-rostock.de>
Date: Mon, 11 Mar 2024 15:28:23 +0000
Subject: [PATCH] arch-riscv: fix argument handling of syscalls in SE mode

With the previously introduced struct wrapper GuestAddr, the asm
tests fail. This patch substitutes implements SyscallABI32 similar
to RegABI32, i.e., as a struct based on GenericSyscallABI32.
Furthermore, a get function for arguments is implemented for wide
arguments. It returns the lower 32 bits of a register.

Change-Id: I233a67a5d5c15ab0d019a63bc57f1225288e33cc
---
 src/arch/riscv/SConscript     |  1 +
 src/arch/riscv/se_workload.cc | 44 +++++++++++++++++++++++++++++++++++
 src/arch/riscv/se_workload.hh | 22 +++++++++++++++++-
 3 files changed, 66 insertions(+), 1 deletion(-)
 create mode 100644 src/arch/riscv/se_workload.cc

diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 78864523c7..2231a0ffa1 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -58,6 +58,7 @@ Source('pma_checker.cc', tags='riscv isa')
 Source('pmp.cc', tags='riscv isa')
 Source('reg_abi.cc', tags='riscv isa')
 Source('remote_gdb.cc', tags='riscv isa')
+Source('se_workload.cc', tags='riscv isa')
 Source('tlb.cc', tags='riscv isa')
 
 Source('linux/se_workload.cc', tags='riscv isa')
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/se_workload.cc
new file mode 100644
index 0000000000..108bea9d86
--- /dev/null
+++ b/src/arch/riscv/se_workload.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2020 Google Inc.
+ * Copyright (c) 2024 University of Rostock
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <arch/riscv/se_workload.hh>
+
+namespace gem5
+{
+
+namespace RiscvISA
+{
+
+const std::vector<RegId> SEWorkload::SyscallABI32::ArgumentRegs = {
+    int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
+    int_reg::A4, int_reg::A5, int_reg::A6
+};
+
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index dd18a92905..8357ab5ac6 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright 2020 Google Inc.
+ * Copyright (c) 2024 University of Rostock
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -61,7 +62,12 @@ class SEWorkload : public gem5::SEWorkload
     loader::Arch getArch() const override { return loader::Riscv64; }
 
     using SyscallABI64 = RegABI64;
-    using SyscallABI32 = RegABI32;
+
+    struct SyscallABI32 : public GenericSyscallABI32
+    {
+        static const std::vector<RegId> ArgumentRegs;
+    };
+
 };
 
 } // namespace RiscvISA
@@ -69,6 +75,20 @@ class SEWorkload : public gem5::SEWorkload
 namespace guest_abi
 {
 
+template<typename ABI, typename Arg>
+struct Argument<ABI, Arg,
+    std::enable_if_t<
+        std::is_base_of_v<ABI, RiscvISA::SEWorkload::SyscallABI32> &&
+        std::is_integral_v<Arg> &&
+        ABI::template IsWideV<Arg>>>
+{
+    static Arg
+    get(ThreadContext *tc, typename ABI::State &state)
+    {
+        return (Arg) bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
+    }
+};
+
 template <>
 struct Result<RiscvISA::SEWorkload::SyscallABI64, SyscallReturn>
 {