From d32c140bde4b1c0cc816f0922f2e1ef7e57717f5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 18 Jan 2021 01:10:54 -0800 Subject: [PATCH] arch,cpu: Move the inUserMode function to the ISA object. This function is used when tracing execution with --debug-flags=Exec. The data used by the function (now method) is stored in the ISA object, and so that's a logical place to move it. Change-Id: I624f9365124679343e988cabfb4e1929225b439a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39323 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/fastmodel/iris/isa.hh | 8 ++++++++ src/arch/arm/isa.hh | 8 ++++++++ src/arch/arm/utility.hh | 12 ------------ src/arch/generic/isa.hh | 1 + src/arch/mips/isa.hh | 20 ++++++++++++++++++++ src/arch/mips/utility.hh | 16 ---------------- src/arch/power/isa.hh | 6 ++++++ src/arch/power/utility.hh | 6 ------ src/arch/riscv/isa.hh | 2 ++ src/arch/riscv/utility.hh | 6 ------ src/arch/sparc/isa.hh | 8 ++++++++ src/arch/sparc/utility.hh | 8 -------- src/arch/x86/isa.hh | 7 +++++++ src/arch/x86/utility.hh | 11 ----------- src/cpu/exetrace.cc | 12 ++++++------ 15 files changed, 66 insertions(+), 65 deletions(-) diff --git a/src/arch/arm/fastmodel/iris/isa.hh b/src/arch/arm/fastmodel/iris/isa.hh index d9646df23c..a7ae7b52d6 100644 --- a/src/arch/arm/fastmodel/iris/isa.hh +++ b/src/arch/arm/fastmodel/iris/isa.hh @@ -28,6 +28,7 @@ #ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__ #define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__ +#include "arch/arm/utility.hh" #include "arch/generic/isa.hh" namespace Iris @@ -39,6 +40,13 @@ class ISA : public BaseISA ISA(const Params &p) : BaseISA(p) {} void serialize(CheckpointOut &cp) const; + + bool + inUserMode() const override + { + CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); + return ::inUserMode(cpsr); + } }; } // namespace Iris diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index dd4dc6e830..7888229cac 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -48,6 +48,7 @@ #include "arch/arm/system.hh" #include "arch/arm/tlb.hh" #include "arch/arm/types.hh" +#include "arch/arm/utility.hh" #include "arch/generic/isa.hh" #include "arch/generic/traits.hh" #include "debug/Checkpoint.hh" @@ -891,6 +892,13 @@ namespace ArmISA { return readMiscRegNoEffect(MISCREG_CONTEXTIDR); } + + bool + inUserMode() const override + { + CPSR cpsr = miscRegs[MISCREG_CPSR]; + return ArmISA::inUserMode(cpsr); + } }; } diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index e255b1c5b9..bd043df914 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -110,24 +110,12 @@ inUserMode(CPSR cpsr) return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T; } -static inline bool -inUserMode(ThreadContext *tc) -{ - return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); -} - static inline bool inPrivilegedMode(CPSR cpsr) { return !inUserMode(cpsr); } -static inline bool -inPrivilegedMode(ThreadContext *tc) -{ - return !inUserMode(tc); -} - bool isSecure(ThreadContext *tc); bool inAArch64(ThreadContext *tc); diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index 7d5daa84ce..4c717c71db 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -56,6 +56,7 @@ class BaseISA : public SimObject virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; } virtual uint64_t getExecutingAsid() const { return 0; } + virtual bool inUserMode() const = 0; }; #endif // __ARCH_GENERIC_ISA_HH__ diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index 1e94a98e6b..cc05781404 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -140,6 +140,26 @@ namespace MipsISA // dummy int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } + + bool + inUserMode() const override + { + RegVal Stat = readMiscRegNoEffect(MISCREG_STATUS); + RegVal Dbg = readMiscRegNoEffect(MISCREG_DEBUG); + + if (// EXL, ERL or CU0 set, CP0 accessible + (Stat & 0x10000006) == 0 && + // DM bit set, CP0 accessible + (Dbg & 0x40000000) == 0 && + // KSU = 0, kernel mode is base mode + (Stat & 0x00000018) != 0) { + // Unable to use Status_CU0, etc directly, + // using bitfields & masks. + return true; + } else { + return false; + } + } }; } diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 0cb9349c3f..6fb211def7 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -65,22 +65,6 @@ bool isNan(void *val_ptr, int size); bool isQnan(void *val_ptr, int size); bool isSnan(void *val_ptr, int size); -static inline bool -inUserMode(ThreadContext *tc) -{ - RegVal Stat = tc->readMiscReg(MISCREG_STATUS); - RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG); - - if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible - (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible - (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode - // Unable to use Status_CU0, etc directly, using bitfields & masks - return true; - } else { - return false; - } -} - //////////////////////////////////////////////////////////////////////// // // Translation stuff diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 076cbc855d..3f7968ebde 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -126,6 +126,12 @@ class ISA : public BaseISA return reg; } + bool + inUserMode() const override + { + return false; + } + using Params = PowerISAParams; ISA(const Params &p); diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index 9092a233a7..bdb201d23d 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -58,12 +58,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst) pc.advance(); } -static inline bool -inUserMode(ThreadContext *tc) -{ - return 0; -} - } // namespace PowerISA diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index dbcb206202..1c5dac3c42 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -95,6 +95,8 @@ class ISA : public BaseISA int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } + bool inUserMode() const override { return true; } + void serialize(CheckpointOut &cp) const; void unserialize(CheckpointIn &cp); diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh index c2f4ac8e36..32cf0464fc 100644 --- a/src/arch/riscv/utility.hh +++ b/src/arch/riscv/utility.hh @@ -157,12 +157,6 @@ advancePC(PCState &pc, const StaticInstPtr &inst) inst->advancePC(pc); } -static inline bool -inUserMode(ThreadContext *tc) -{ - return true; -} - } // namespace RiscvISA #endif // __ARCH_RISCV_UTILITY_HH__ diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 077c649a52..a58cd8599f 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -223,6 +223,14 @@ class ISA : public BaseISA using Params = SparcISAParams; + bool + inUserMode() const override + { + PSTATE pstate = readMiscRegNoEffect(MISCREG_PSTATE); + HPSTATE hpstate = readMiscRegNoEffect(MISCREG_HPSTATE); + return !(pstate.priv || hpstate.hpriv); + } + ISA(const Params &p); }; } diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 18b5164795..8ec3e10118 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -50,14 +50,6 @@ buildRetPC(const PCState &curPC, const PCState &callPC) return ret; } -static inline bool -inUserMode(ThreadContext *tc) -{ - PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); - HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); - return !(pstate.priv || hpstate.hpriv); -} - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 8bd3072dc4..cc65563a49 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -103,6 +103,13 @@ namespace X86ISA int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } + bool + inUserMode() const override + { + HandyM5Reg m5reg = readMiscRegNoEffect(MISCREG_M5_REG); + return m5reg.cpl == 3; + } + void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1ff7b1612f..79274ca577 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -53,17 +53,6 @@ namespace X86ISA return retPC; } - static inline bool - inUserMode(ThreadContext *tc) - { - if (!FullSystem) { - return true; - } else { - HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); - return m5reg.cpl == 3; - } - } - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index e144743397..76db4d7b8d 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -60,11 +60,11 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) { std::stringstream outs; - if (!Debug::ExecUser || !Debug::ExecKernel) { - bool in_user_mode = TheISA::inUserMode(thread); - if (in_user_mode && !Debug::ExecUser) return; - if (!in_user_mode && !Debug::ExecKernel) return; - } + const bool in_user_mode = thread->getIsaPtr()->inUserMode(); + if (in_user_mode && !Debug::ExecUser) + return; + if (!in_user_mode && !Debug::ExecKernel) + return; if (Debug::ExecAsid) { outs << "A" << std::dec << @@ -77,7 +77,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) Addr cur_pc = pc.instAddr(); Loader::SymbolTable::const_iterator it; ccprintf(outs, "%#x", cur_pc); - if (Debug::ExecSymbol && (!FullSystem || !TheISA::inUserMode(thread)) && + if (Debug::ExecSymbol && (!FullSystem || !in_user_mode) && (it = Loader::debugSymbolTable.findNearest(cur_pc)) != Loader::debugSymbolTable.end()) { Addr delta = cur_pc - it->address;