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mem: Modify DRAM controller for flexibility and new memories

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This change includes:
1) Verify available command bandwidth
2) Add support for multi-cycle commands
3) Add new timing parameters
4) Add ability to interleave bursts
5) Add LPDDR5 configurations

The DRAM controller historically does not verify contention on the
command bus and if there is adaquate command bandwidth to issue a
new command. As memory technologies evolve, multiple cycles are becoming
a requirement for some commands.  Depending on the burst length, this
can stress the command bandwidth. A check was added to verify command
issue does not exceed a maximum value within a defined window. The
default window is a burst, with the maximum value defined based on the
burst length and media clocking characteristics. When the command bandwidth
is exceeded, commands will be shifted to subsequent burst windows.

Added support for multi-cycle commands, specifically Activate, which
requires a larger address width as capacities grow.  Additionally,
added support for multi-cycle Read / Write bursts for low power
DRAM cases in which additional CLK synchronization may be required
to run at higher speeds.

To support emerging memories, added the following new timing parameters.
1) tPPD -- Precharge-to-Precharge delay
2) tAAD -- Max delay between Activate-1 and Activate-2 commands

I/O data rates are continuing to increase for DRAM but the core frequency
is still fairly stagnant for many technologies. As we increase the burst
length, either the core prefetch needs to increase (for a seamless burst)
or the burst will be transferred with gaps on the data bus. To support
the latter case, added the ability to interleave 2 bursts across bank
groups.

Using the changes above, added an initial set of LPDDR5 configurations.

Change-Id: I1b14fed221350e6e403f7cbf089fe6c7f033c181
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26236
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Wendy Elsasser
2019-05-21 14:38:53 -05:00
parent b4f4b33ada
commit d228a283c9
5 changed files with 624 additions and 56 deletions
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13
configs/dram/sweep.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2014-2015, 2018-2019 ARM Limited
# Copyright (c) 2014-2015, 2018-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -146,7 +146,8 @@ page_size = system.mem_ctrls[0].devices_per_rank.value * \
# match the maximum bandwidth of the memory, the parameter is in seconds
# and we need it in ticks (ps)
itt = system.mem_ctrls[0].tBURST.value * 1000000000000
itt = getattr(system.mem_ctrls[0].tBURST_MIN, 'value',
system.mem_ctrls[0].tBURST.value) * 1000000000000
# assume we start at 0
max_addr = mem_range.end
@@ -180,8 +181,8 @@ m5.instantiate()
def trace():
addr_map = ObjectList.dram_addr_map_list.get(options.addr_map)
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
for stride_size in range(burst_size, max_stride + 1, burst_size):
for stride_size in range(burst_size, max_stride + 1, burst_size):
for bank in range(1, nbr_banks + 1):
num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
yield generator(period,
0, max_addr, burst_size, int(itt), int(itt),
@@ -194,5 +195,5 @@ system.tgen.start(trace())
m5.simulate()
print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
(burst_size, nbr_banks, max_stride))
print("DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
generation period: %d" % (burst_size, nbr_banks, max_stride, itt))