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cpu: Remove alpha specialized code.

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Change-Id: I770132af2f11ed232a100ab8bef942f17789ef36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24648
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-01-22 21:36:09 -08:00
parent 67273d65ed
commit d1fd4311b4
9 changed files with 8 additions and 43 deletions
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6
src/cpu/BaseCPU.py
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@@ -62,11 +62,7 @@ from m5.objects.Platform import Platform
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
from m5.objects.AlphaISA import AlphaISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'sparc':
if buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA