From d1ed308af8a5dff7fc0dde304b8bb3bfef8b29c3 Mon Sep 17 00:00:00 2001 From: Jason Lowe-Power Date: Wed, 30 Mar 2022 18:15:01 -0700 Subject: [PATCH] stdlib,mem-ruby: Use protocol-spec. names Update the standard library Ruby protocols to use the protocol-specific class names instead of the deprecated general names. Unfortunately, some code became duplicated between similar controllers. I tried multiple inheritance, but it didn't work out for me. I think the correct solution is to move some of the shared code down into the generated python. That's out of the scope for these changes. Change-Id: I3444bee3c2917dcbe92b600b85e60244129aad35 Signed-off-by: Jason Lowe-Power --- src/python/SConscript | 8 --- .../ruby/caches/abstract_directory.py | 50 --------------- .../ruby/caches/abstract_dma_controller.py | 49 -------------- .../ruby/caches/abstract_l1_cache.py | 64 ------------------- .../ruby/caches/abstract_l2_cache.py | 50 --------------- .../ruby/caches/mesi_two_level/directory.py | 20 ++++-- .../caches/mesi_two_level/dma_controller.py | 24 +++++-- .../ruby/caches/mesi_two_level/l1_cache.py | 26 +++++--- .../ruby/caches/mesi_two_level/l2_cache.py | 19 ++++-- .../ruby/caches/mi_example/directory.py | 20 ++++-- .../ruby/caches/mi_example/dma_controller.py | 26 +++++--- .../ruby/caches/mi_example/l1_cache.py | 19 ++++-- 12 files changed, 110 insertions(+), 265 deletions(-) delete mode 100644 src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py delete mode 100644 src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py delete mode 100644 src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py delete mode 100644 src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py diff --git a/src/python/SConscript b/src/python/SConscript index df32583e4a..340a1bab20 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -120,14 +120,6 @@ PySource('gem5.components.cachehierarchies.ruby', 'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py') PySource('gem5.components.cachehierarchies.ruby.caches', 'gem5/components/cachehierarchies/ruby/caches/__init__.py') -PySource('gem5.components.cachehierarchies.ruby.caches', - 'gem5/components/cachehierarchies/ruby/caches/abstract_directory.py') -PySource('gem5.components.cachehierarchies.ruby.caches', - 'gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py') -PySource('gem5.components.cachehierarchies.ruby.caches', - 'gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py') -PySource('gem5.components.cachehierarchies.ruby.caches', - 'gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py') PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', 'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py') PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level', diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py deleted file mode 100644 index 8552b975e1..0000000000 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2021 The Regents of the University of California -# All Rights Reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from abc import abstractmethod - -from m5.objects import Directory_Controller - - -class AbstractDirectory(Directory_Controller): - _version = 0 - - @classmethod - def versionCount(cls): - cls._version += 1 # Use count for this particular type - return cls._version - 1 - - def __init__(self, network, cache_line_size): - """ """ - super().__init__() - self.version = self.versionCount() - self._cache_line_size = cache_line_size - self.connectQueues(network) - - @abstractmethod - def connectQueues(self, network): - """Connect all of the queues for this controller.""" - raise NotImplementedError diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py deleted file mode 100644 index dad1f7cd72..0000000000 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2021 The Regents of the University of California -# All Rights Reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from abc import abstractmethod - -from m5.objects import DMA_Controller - - -class AbstractDMAController(DMA_Controller): - _version = 0 - - @classmethod - def versionCount(cls): - cls._version += 1 # Use count for this particular type - return cls._version - 1 - - def __init__(self, network, cache_line_size): - super().__init__() - self.version = self.versionCount() - self._cache_line_size = cache_line_size - self.connectQueues(network) - - @abstractmethod - def connectQueues(self, network): - """Connect all of the queues for this controller.""" - raise NotImplementedError diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py deleted file mode 100644 index a9944c4d03..0000000000 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py +++ /dev/null @@ -1,64 +0,0 @@ -# Copyright (c) 2021 The Regents of the University of California -# All Rights Reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import math -from abc import abstractmethod - -from m5.objects import L1Cache_Controller - -from .....isas import ISA -from ....processors.abstract_core import AbstractCore -from ....processors.cpu_types import CPUTypes - - -class AbstractL1Cache(L1Cache_Controller): - _version = 0 - - @classmethod - def versionCount(cls): - cls._version += 1 # Use count for this particular type - return cls._version - 1 - - # TODO: I don't love that we have to pass in the cache line size. - # However, we need some way to set the index bits - def __init__(self, network, cache_line_size): - """ """ - super().__init__() - - self.version = self.versionCount() - self._cache_line_size = cache_line_size - self.connectQueues(network) - - def getBlockSizeBits(self): - bits = int(math.log(self._cache_line_size, 2)) - if 2**bits != self._cache_line_size.value: - raise Exception("Cache line size not a power of 2!") - return bits - - @abstractmethod - def connectQueues(self, network): - """Connect all of the queues for this controller.""" - raise NotImplementedError diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py deleted file mode 100644 index 41929f4e42..0000000000 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2021 The Regents of the University of California -# All Rights Reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from abc import abstractmethod - -from m5.objects import L2Cache_Controller - - -class AbstractL2Cache(L2Cache_Controller): - _version = 0 - - @classmethod - def versionCount(cls): - cls._version += 1 # Use count for this particular type - return cls._version - 1 - - def __init__(self, network, cache_line_size): - super().__init__() - - self.version = self.versionCount() - self._cache_line_size = cache_line_size - self.connectQueues(network) - - @abstractmethod - def connectQueues(self, network): - """Connect all of the queues for this controller.""" - raise NotImplementedError diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py index d0c54840fc..13dbc7a747 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py @@ -24,24 +24,34 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + from m5.objects import ( + MESI_Two_Level_Directory_Controller, MessageBuffer, RubyDirectoryMemory, ) -from ......utils.override import overrides -from ..abstract_directory import AbstractDirectory +class Directory(MESI_Two_Level_Directory_Controller): + + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 -class Directory(AbstractDirectory): def __init__(self, network, cache_line_size, mem_range, port): - super().__init__(network, cache_line_size) + super().__init__() + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) + self.addr_ranges = [mem_range] self.directory = RubyDirectoryMemory(block_size=cache_line_size) # Connect this directory to the memory side. self.memory_out_port = port - @overrides(AbstractDirectory) def connectQueues(self, network): self.requestToDir = MessageBuffer() self.requestToDir.in_port = network.out_port diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py index aa7a5ad778..71871242ae 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py @@ -24,17 +24,27 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import MessageBuffer - -from ......utils.override import overrides -from ..abstract_dma_controller import AbstractDMAController +from m5.objects import ( + MESI_Two_Level_DMA_Controller, + MessageBuffer, +) -class DMAController(AbstractDMAController): +class DMAController(MESI_Two_Level_DMA_Controller): + + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 + def __init__(self, network, cache_line_size): - super().__init__(network, cache_line_size) + super().__init__() + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) - @overrides(AbstractDMAController) def connectQueues(self, network): self.mandatoryQueue = MessageBuffer() self.responseFromDir = MessageBuffer(ordered=True) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py index 13625beea7..9f7cc0a61c 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py @@ -28,18 +28,25 @@ import math from m5.objects import ( ClockDomain, + MESI_Two_Level_L1Cache_Controller, MessageBuffer, RubyCache, RubyPrefetcher, ) from ......isas import ISA -from ......utils.override import * from .....processors.abstract_core import AbstractCore -from ..abstract_l1_cache import AbstractL1Cache -class L1Cache(AbstractL1Cache): +class L1Cache(MESI_Two_Level_L1Cache_Controller): + + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 + def __init__( self, l1i_size, @@ -56,29 +63,32 @@ class L1Cache(AbstractL1Cache): """Creating L1 cache controller. Consist of both instruction and data cache. """ - super().__init__(network, cache_line_size) + super().__init__() + + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) # This is the cache memory object that stores the cache data and tags self.L1Icache = RubyCache( size=l1i_size, assoc=l1i_assoc, - start_index_bit=self.getBlockSizeBits(), + start_index_bit=self._cache_line_size, is_icache=True, ) self.L1Dcache = RubyCache( size=l1d_size, assoc=l1d_assoc, - start_index_bit=self.getBlockSizeBits(), + start_index_bit=self._cache_line_size, is_icache=False, ) self.l2_select_num_bits = int(math.log(num_l2Caches, 2)) self.clk_domain = clk_domain - self.prefetcher = RubyPrefetcher(block_size=cache_line_size) + self.prefetcher = RubyPrefetcher(block_size=self._cache_line_size) self.send_evictions = core.requires_send_evicts() self.transitions_per_cycle = 4 self.enable_prefetch = False - @overrides(AbstractL1Cache) def connectQueues(self, network): self.mandatoryQueue = MessageBuffer() self.requestFromL1Cache = MessageBuffer() diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py index 4f7c923c54..0c6b9a57e0 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py @@ -27,19 +27,29 @@ import math from m5.objects import ( + MESI_Two_Level_L2Cache_Controller, MessageBuffer, RubyCache, ) -from ......utils.override import * -from ..abstract_l2_cache import AbstractL2Cache +class L2Cache(MESI_Two_Level_L2Cache_Controller): + + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 -class L2Cache(AbstractL2Cache): def __init__( self, l2_size, l2_assoc, network, num_l2Caches, cache_line_size ): - super().__init__(network, cache_line_size) + super().__init__() + + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) # This is the cache memory object that stores the cache data and tags self.L2cache = RubyCache( @@ -55,7 +65,6 @@ class L2Cache(AbstractL2Cache): bits = int(math.log(self._cache_line_size, 2)) + l2_bits return bits - @overrides(AbstractL2Cache) def connectQueues(self, network): self.DirRequestFromL2Cache = MessageBuffer() self.DirRequestFromL2Cache.out_port = network.in_port diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py index 79e40e9e01..a60a55c338 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py @@ -26,26 +26,34 @@ from m5.objects import ( MessageBuffer, + MI_example_Directory_Controller, RubyDirectoryMemory, ) -from ......utils.override import overrides -from ..abstract_directory import AbstractDirectory - -class Directory(AbstractDirectory): +class Directory(MI_example_Directory_Controller): """ The directory controller for the MI_Example cache hierarchy. """ + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 + def __init__(self, network, cache_line_size, mem_range, port): - super().__init__(network, cache_line_size) + super().__init__() + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) + self.addr_ranges = [mem_range] self.directory = RubyDirectoryMemory(block_size=cache_line_size) # Connect this directory to the memory side. self.memory_out_port = port - @overrides(AbstractDirectory) def connectQueues(self, network): self.requestToDir = MessageBuffer(ordered=True) self.requestToDir.in_port = network.out_port diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py index b9c1f4a60f..21f6364e48 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py @@ -24,22 +24,30 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.objects import MessageBuffer - -from ......utils.override import overrides -from ..abstract_dma_controller import AbstractDMAController +from m5.objects import ( + MessageBuffer, + MI_example_DMA_Controller, +) -class DMAController(AbstractDMAController): +class DMAController(MI_example_DMA_Controller): """ A DMA Controller for use in the MI_Example cache hierarchy setup. """ - class DMAController(AbstractDMAController): - def __init__(self, network, cache_line_size): - super().__init__(network, cache_line_size) + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 + + def __init__(self, network, cache_line_size): + super().__init__() + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) - @overrides(AbstractDMAController) def connectQueues(self, network): self.mandatoryQueue = MessageBuffer() self.requestToDir = MessageBuffer() diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py index 2feae222d8..1deca14986 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py @@ -27,16 +27,24 @@ from m5.objects import ( ClockDomain, MessageBuffer, + MI_example_L1Cache_Controller, RubyCache, ) from ......isas import ISA from ......utils.override import overrides from .....processors.abstract_core import AbstractCore -from ..abstract_l1_cache import AbstractL1Cache -class L1Cache(AbstractL1Cache): +class L1Cache(MI_example_L1Cache_Controller): + + _version = 0 + + @classmethod + def versionCount(cls): + cls._version += 1 # Use count for this particular type + return cls._version - 1 + def __init__( self, size: str, @@ -47,10 +55,13 @@ class L1Cache(AbstractL1Cache): target_isa: ISA, clk_domain: ClockDomain, ): - super().__init__(network, cache_line_size) + super().__init__() + self.version = self.versionCount() + self._cache_line_size = cache_line_size + self.connectQueues(network) self.cacheMemory = RubyCache( - size=size, assoc=assoc, start_index_bit=self.getBlockSizeBits() + size=size, assoc=assoc, start_index_bit=self._cache_line_size ) self.clk_domain = clk_domain