arch-arm: Make TLB misses from a sw prefetch visible

While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.

This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss

Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/tlb.cc

@@ -1583,6 +1583,14 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
     *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el,
                  false);
     if (*te == NULL) {
+        // Note, we are updating the stats for sw prefetching misses as well
+        if (is_fetch)
+            stats.instMisses++;
+        else if (is_write)
+            stats.writeMisses++;
+        else
+            stats.readMisses++;
+
         if (req->isPrefetch()) {
             // if the request is a prefetch don't attempt to fill the TLB or go
             // any further with the memory access (here we can safely use the
@@ -1592,13 +1600,6 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
                vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2);
         }
 
-        if (is_fetch)
-            stats.instMisses++;
-        else if (is_write)
-            stats.writeMisses++;
-        else
-            stats.readMisses++;
-
         // start translation table walk, pass variables rather than
         // re-retreaving in table walker for speed
         DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",