diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 4979f7d86f..61c6a304d7 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -87,7 +87,7 @@ def config_cache(options, system): dcache_class, icache_class, l2_cache_class, walk_cache_class = \ core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \ core.O3_ARM_v7aL2, \ - core.O3_ARM_v7aWalkCache + None elif options.cpu_type == "HPI": try: import cores.arm.HPI as core @@ -96,7 +96,7 @@ def config_cache(options, system): sys.exit(1) dcache_class, icache_class, l2_cache_class, walk_cache_class = \ - core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache + core.HPI_DCache, core.HPI_ICache, core.HPI_L2, None else: dcache_class, icache_class, l2_cache_class, walk_cache_class = \ L1_DCache, L1_ICache, L2Cache, None diff --git a/configs/example/arm/baremetal.py b/configs/example/arm/baremetal.py index 9655bb165a..094434495b 100644 --- a/configs/example/arm/baremetal.py +++ b/configs/example/arm/baremetal.py @@ -61,14 +61,12 @@ import workloads # the cache class may be 'None' if the particular cache is not present. cpu_types = { - "atomic" : ( AtomicSimpleCPU, None, None, None, None), + "atomic" : ( AtomicSimpleCPU, None, None, None), "minor" : (MinorCPU, devices.L1I, devices.L1D, - devices.WalkCache, devices.L2), "hpi" : ( HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, - HPI.HPI_WalkCache, HPI.HPI_L2) } diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 73aea59a1c..5217b08729 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -106,12 +106,11 @@ class MemBus(SystemXBar): class CpuCluster(SubSystem): def __init__(self, system, num_cpus, cpu_clock, cpu_voltage, - cpu_type, l1i_type, l1d_type, wcache_type, l2_type): + cpu_type, l1i_type, l1d_type, l2_type): super(CpuCluster, self).__init__() self._cpu_type = cpu_type self._l1i_type = l1i_type self._l1d_type = l1d_type - self._wcache_type = wcache_type self._l2_type = l2_type assert num_cpus > 0 @@ -140,9 +139,7 @@ class CpuCluster(SubSystem): for cpu in self.cpus: l1i = None if self._l1i_type is None else self._l1i_type() l1d = None if self._l1d_type is None else self._l1d_type() - iwc = None if self._wcache_type is None else self._wcache_type() - dwc = None if self._wcache_type is None else self._wcache_type() - cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc) + cpu.addPrivateSplitL1Caches(l1i, l1d) def addL2(self, clk_domain): if self._l2_type is None: diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index c590fe510f..3f8b0cfb19 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -79,7 +79,7 @@ class BigCluster(devices.CpuCluster): def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): cpu_config = [ ObjectList.cpu_list.get("O3_ARM_v7a_3"), - devices.L1I, devices.L1D, devices.WalkCache, devices.L2 ] + devices.L1I, devices.L1D, devices.L2 ] super(BigCluster, self).__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config) @@ -87,7 +87,7 @@ class LittleCluster(devices.CpuCluster): def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): cpu_config = [ ObjectList.cpu_list.get("MinorCPU"), devices.L1I, - devices.L1D, devices.WalkCache, devices.L2 ] + devices.L1D, devices.L2 ] super(LittleCluster, self).__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config) @@ -95,7 +95,7 @@ class Ex5BigCluster(devices.CpuCluster): def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): cpu_config = [ ObjectList.cpu_list.get("ex5_big"), ex5_big.L1I, - ex5_big.L1D, ex5_big.WalkCache, ex5_big.L2 ] + ex5_big.L1D, ex5_big.L2 ] super(Ex5BigCluster, self).__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config) @@ -103,7 +103,7 @@ class Ex5LittleCluster(devices.CpuCluster): def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): cpu_config = [ ObjectList.cpu_list.get("ex5_LITTLE"), - ex5_LITTLE.L1I, ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, + ex5_LITTLE.L1I, ex5_LITTLE.L1D, ex5_LITTLE.L2 ] super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config) diff --git a/configs/example/arm/ruby_fs.py b/configs/example/arm/ruby_fs.py index 3783f3389e..d820f86316 100644 --- a/configs/example/arm/ruby_fs.py +++ b/configs/example/arm/ruby_fs.py @@ -62,14 +62,12 @@ default_root_device = '/dev/vda1' # the cache class may be 'None' if the particular cache is not present. cpu_types = { - "noncaching" : ( NonCachingSimpleCPU, None, None, None, None), + "noncaching" : ( NonCachingSimpleCPU, None, None, None), "minor" : (MinorCPU, devices.L1I, devices.L1D, - devices.WalkCache, devices.L2), "hpi" : ( HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, - HPI.HPI_WalkCache, HPI.HPI_L2) } diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py index 11190dbd6d..40e645b564 100644 --- a/configs/example/arm/starter_fs.py +++ b/configs/example/arm/starter_fs.py @@ -65,14 +65,12 @@ default_root_device = '/dev/vda1' # the cache class may be 'None' if the particular cache is not present. cpu_types = { - "atomic" : ( AtomicSimpleCPU, None, None, None, None), + "atomic" : ( AtomicSimpleCPU, None, None, None), "minor" : (MinorCPU, devices.L1I, devices.L1D, - devices.WalkCache, devices.L2), "hpi" : ( HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, - HPI.HPI_WalkCache, HPI.HPI_L2) } diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 82fc49e5c6..d80f7498d6 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -59,14 +59,12 @@ import devices # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of # the cache class may be 'None' if the particular cache is not present. cpu_types = { - "atomic" : ( AtomicSimpleCPU, None, None, None, None), + "atomic" : ( AtomicSimpleCPU, None, None, None), "minor" : (MinorCPU, devices.L1I, devices.L1D, - devices.WalkCache, devices.L2), "hpi" : ( HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, - HPI.HPI_WalkCache, HPI.HPI_L2) }