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misc: Move Mode and Translation from BaseTLB to BaseMMU

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This is a step towards moving most of the TLB logic to the
MMU class.

Change-Id: Id6b1fb30aa89960705f165f9738f5b50aa1e6bdb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46779
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-06-10 14:58:41 +01:00
parent d58b4f004e
commit d1cdcb311b
68 changed files with 550 additions and 483 deletions
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2
src/cpu/base.cc
View File

@@ -258,7 +258,7 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
req->setVirt(addr, size, 0x0, dataRequestorId(), tc->instAddr());
// translate to physical address
Fault fault = mmu->translateAtomic(req, tc, BaseTLB::Read);
Fault fault = mmu->translateAtomic(req, tc, BaseMMU::Read);
assert(fault == NoFault);
monitor.pAddr = req->getPaddr() & mask;

4
src/cpu/checker/cpu.cc
View File

@@ -190,7 +190,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
// translate to physical address
if (predicate) {
fault = mmu->translateFunctional(mem_req, tc, BaseTLB::Read);
fault = mmu->translateFunctional(mem_req, tc, BaseMMU::Read);
}
if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
@@ -274,7 +274,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
predicate = (mem_req != nullptr);
if (predicate) {
fault = mmu->translateFunctional(mem_req, tc, BaseTLB::Write);
fault = mmu->translateFunctional(mem_req, tc, BaseMMU::Write);
}
if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {

2
src/cpu/checker/cpu_impl.hh
View File

@@ -245,7 +245,7 @@ Checker<DynInstPtr>::verify(const DynInstPtr &completed_inst)
thread->instAddr());
fault = mmu->translateFunctional(
mem_req, tc, BaseTLB::Execute);
mem_req, tc, BaseMMU::Execute);
if (fault != NoFault) {
if (unverifiedInst->getFault() == NoFault) {

4
src/cpu/kvm/base.cc
View File

@@ -1089,8 +1089,8 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write)
// before they are inserted into the memory system. This enables
// APIC accesses on x86 and m5ops where supported through a MMIO
// interface.
BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
Fault fault(tc->getMMUPtr()->finalizePhysical(mmio_req, tc, tlb_mode));
BaseMMU::Mode access_type(write ? BaseMMU::Write : BaseMMU::Read);
Fault fault(tc->getMMUPtr()->finalizePhysical(mmio_req, tc, access_type));
if (fault != NoFault)
warn("Finalization of MMIO address failed: %s\n", fault->name());

4
src/cpu/minor/fetch1.cc
View File

@@ -193,7 +193,7 @@ Fetch1::fetchLine(ThreadID tid)
cpu.threads[request->id.threadId]->mmu->translateTiming(
request->request,
cpu.getContext(request->id.threadId),
request, BaseTLB::Execute);
request, BaseMMU::Execute);
lineSeqNum++;
@@ -234,7 +234,7 @@ Fetch1::FetchRequest::makePacket()
void
Fetch1::FetchRequest::finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode)
ThreadContext *tc, BaseMMU::Mode mode)
{
fault = fault_;

7
src/cpu/minor/fetch1.hh
View File

@@ -47,6 +47,7 @@
#include <vector>
#include "arch/generic/mmu.hh"
#include "base/named.hh"
#include "cpu/base.hh"
#include "cpu/minor/buffers.hh"
@@ -104,7 +105,7 @@ class Fetch1 : public Named
/** Structure to hold SenderState info through
* translation and memory accesses. */
class FetchRequest :
public BaseTLB::Translation, /* For TLB lookups */
public BaseMMU::Translation, /* For TLB lookups */
public Packet::SenderState /* For packing into a Packet */
{
protected:
@@ -159,7 +160,7 @@ class Fetch1 : public Named
bool isComplete() const { return state == Complete; }
protected:
/** BaseTLB::Translation interface */
/** BaseMMU::Translation interface */
/** Interface for ITLB responses. We can handle delay, so don't
* do anything */
@@ -169,7 +170,7 @@ class Fetch1 : public Named
* the request on to the ports' handleTLBResponse member
* function */
void finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode);
ThreadContext *tc, BaseMMU::Mode mode);
public:
FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :

8
src/cpu/minor/lsq.cc
View File

@@ -272,7 +272,7 @@ LSQ::clearMemBarrier(MinorDynInstPtr inst)
void
LSQ::SingleDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode)
ThreadContext *tc, BaseMMU::Mode mode)
{
port.numAccessesInDTLB--;
@@ -317,7 +317,7 @@ LSQ::SingleDataRequest::startAddrTranslation()
* finish/markDelayed on the LSQRequest as it bears the Translation
* interface */
thread->getMMUPtr()->translateTiming(
request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
request, thread, this, (isLoad ? BaseMMU::Read : BaseMMU::Write));
} else {
disableMemAccess();
setState(LSQ::LSQRequest::Complete);
@@ -335,7 +335,7 @@ LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
void
LSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode)
ThreadContext *tc, BaseMMU::Mode mode)
{
port.numAccessesInDTLB--;
@@ -716,7 +716,7 @@ LSQ::SplitDataRequest::sendNextFragmentToTranslation()
thread->getMMUPtr()->translateTiming(
fragmentRequests[fragment_index], thread, this, (isLoad ?
BaseTLB::Read : BaseTLB::Write));
BaseMMU::Read : BaseMMU::Write));
}
bool

10
src/cpu/minor/lsq.hh
View File

@@ -127,7 +127,7 @@ class LSQ : public Named
* translation, the queues in this port and back from the memory
* system. */
class LSQRequest :
public BaseTLB::Translation, /* For TLB lookups */
public BaseMMU::Translation, /* For TLB lookups */
public Packet::SenderState /* For packing into a Packet */
{
public:
@@ -196,7 +196,7 @@ class LSQ : public Named
LSQRequestState state;
protected:
/** BaseTLB::Translation interface */
/** BaseMMU::Translation interface */
void markDelayed() { isTranslationDelayed = true; }
/** Instructions may want to suppress translation faults (e.g.
@@ -292,7 +292,7 @@ class LSQ : public Named
protected:
/** TLB interace */
void finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode)
ThreadContext *tc, BaseMMU::Mode mode)
{ }
public:
@@ -353,7 +353,7 @@ class LSQ : public Named
protected:
/** TLB interace */
void finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode);
ThreadContext *tc, BaseMMU::Mode mode);
/** Has my only packet been sent to the memory system but has not
* yet been responded to */
@@ -426,7 +426,7 @@ class LSQ : public Named
protected:
/** TLB response interface */
void finish(const Fault &fault_, const RequestPtr &request_,
ThreadContext *tc, BaseTLB::Mode mode);
ThreadContext *tc, BaseMMU::Mode mode);
public:
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,

2
src/cpu/o3/fetch.cc
View File

@@ -596,7 +596,7 @@ Fetch::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
fetchStatus[tid] = ItlbWait;
FetchTranslation *trans = new FetchTranslation(this);
cpu->mmu->translateTiming(mem_req, cpu->thread[tid]->getTC(),
trans, BaseTLB::Execute);
trans, BaseMMU::Execute);
return true;
}

7
src/cpu/o3/fetch.hh
View File

@@ -42,6 +42,7 @@
#define __CPU_O3_FETCH_HH__
#include "arch/decoder.hh"
#include "arch/generic/mmu.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
@@ -101,7 +102,7 @@ class Fetch
virtual void recvReqRetry();
};
class FetchTranslation : public BaseTLB::Translation
class FetchTranslation : public BaseMMU::Translation
{
protected:
Fetch *fetch;
@@ -113,9 +114,9 @@ class Fetch
void
finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext *tc, BaseTLB::Mode mode)
gem5::ThreadContext *tc, BaseMMU::Mode mode)
{
assert(mode == BaseTLB::Execute);
assert(mode == BaseMMU::Execute);
fetch->finishTranslation(fault, req);
delete this;
}

8
src/cpu/o3/lsq.cc
View File

@@ -859,7 +859,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
void
LSQ::SingleDataRequest::finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode)
gem5::ThreadContext* tc, BaseMMU::Mode mode)
{
_fault.push_back(fault);
numInTranslationFragments = 0;
@@ -891,7 +891,7 @@ LSQ::SingleDataRequest::finish(const Fault &fault, const RequestPtr &req,
void
LSQ::SplitDataRequest::finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode)
gem5::ThreadContext* tc, BaseMMU::Mode mode)
{
int i;
for (i = 0; i < _requests.size() && _requests[i] != req; i++);
@@ -1117,7 +1117,7 @@ LSQ::LSQRequest::sendFragmentToTranslation(int i)
{
numInTranslationFragments++;
_port.getMMUPtr()->translateTiming(request(i), _inst->thread->getTC(),
this, isLoad() ? BaseTLB::Read : BaseTLB::Write);
this, isLoad() ? BaseMMU::Read : BaseMMU::Write);
}
bool
@@ -1415,7 +1415,7 @@ LSQ::HtmCmdRequest::initiateTranslation()
void
LSQ::HtmCmdRequest::finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode)
gem5::ThreadContext* tc, BaseMMU::Mode mode)
{
panic("unexpected behaviour");
}

9
src/cpu/o3/lsq.hh
View File

@@ -49,6 +49,7 @@
#include <queue>
#include <vector>
#include "arch/generic/mmu.hh"
#include "arch/generic/tlb.hh"
#include "base/flags.hh"
#include "base/types.hh"
@@ -227,7 +228,7 @@ class LSQ
*
*
*/
class LSQRequest : public BaseTLB::Translation
class LSQRequest : public BaseMMU::Translation
{
protected:
typedef uint32_t FlagsStorage;
@@ -667,7 +668,7 @@ class LSQ
virtual ~SingleDataRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode);
gem5::ThreadContext* tc, BaseMMU::Mode mode);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void sendPacketToCache();
virtual void buildPackets();
@@ -701,7 +702,7 @@ class LSQ
virtual ~HtmCmdRequest() {}
virtual void initiateTranslation();
virtual void finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode);
gem5::ThreadContext* tc, BaseMMU::Mode mode);
virtual std::string name() const { return "HtmCmdRequest"; }
};
@@ -767,7 +768,7 @@ class LSQ
}
}
virtual void finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseTLB::Mode mode);
gem5::ThreadContext* tc, BaseMMU::Mode mode);
virtual bool recvTimingResp(PacketPtr pkt);
virtual void initiateTranslation();
virtual void sendPacketToCache();

8
src/cpu/simple/atomic.cc
View File

@@ -388,7 +388,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned size,
// translate to physical address
if (predicate) {
fault = thread->mmu->translateAtomic(req, thread->getTC(),
BaseTLB::Read);
BaseMMU::Read);
}
// Now do the access.
@@ -474,7 +474,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
// translate to physical address
if (predicate)
fault = thread->mmu->translateAtomic(req, thread->getTC(),
BaseTLB::Write);
BaseMMU::Write);
// Now do the access.
if (predicate && fault == NoFault) {
@@ -579,7 +579,7 @@ AtomicSimpleCPU::amoMem(Addr addr, uint8_t* data, unsigned size,
// translate to physical address
Fault fault = thread->mmu->translateAtomic(
req, thread->getTC(), BaseTLB::Write);
req, thread->getTC(), BaseMMU::Write);
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
@@ -656,7 +656,7 @@ AtomicSimpleCPU::tick()
ifetch_req->taskId(taskId());
setupFetchRequest(ifetch_req);
fault = thread->mmu->translateAtomic(ifetch_req, thread->getTC(),
BaseTLB::Execute);
BaseMMU::Execute);
}
if (fault == NoFault) {

12
src/cpu/simple/timing.cc
View File

@@ -458,7 +458,7 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
Fault fault;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
BaseMMU::Mode mode = BaseMMU::Read;
if (traceData)
traceData->setMem(addr, size, flags);
@@ -532,7 +532,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
uint8_t *newData = new uint8_t[size];
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
BaseMMU::Mode mode = BaseMMU::Write;
if (data == NULL) {
assert(flags & Request::STORE_NO_DATA);
@@ -596,7 +596,7 @@ TimingSimpleCPU::initiateMemAMO(Addr addr, unsigned size,
Fault fault;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
BaseMMU::Mode mode = BaseMMU::Write;
if (traceData)
traceData->setMem(addr, size, flags);
@@ -662,10 +662,10 @@ TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
} else {
if (!state->isSplit) {
sendData(state->mainReq, state->data, state->res,
state->mode == BaseTLB::Read);
state->mode == BaseMMU::Read);
} else {
sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
state->data, state->mode == BaseTLB::Read);
state->data, state->mode == BaseMMU::Read);
}
}
@@ -705,7 +705,7 @@ TimingSimpleCPU::fetch()
setupFetchRequest(ifetch_req);
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
thread->mmu->translateTiming(ifetch_req, thread->getTC(),
&fetchTranslation, BaseTLB::Execute);
&fetchTranslation, BaseMMU::Execute);
} else {
_status = IcacheWaitResponse;
completeIfetch(NULL);

5
src/cpu/simple/timing.hh
View File

@@ -41,6 +41,7 @@
#ifndef __CPU_SIMPLE_TIMING_HH__
#define __CPU_SIMPLE_TIMING_HH__
#include "arch/generic/mmu.hh"
#include "cpu/simple/base.hh"
#include "cpu/simple/exec_context.hh"
#include "cpu/translation.hh"
@@ -107,7 +108,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
}
};
class FetchTranslation : public BaseTLB::Translation
class FetchTranslation : public BaseMMU::Translation
{
protected:
TimingSimpleCPU *cpu;
@@ -126,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void
finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
BaseTLB::Mode mode)
BaseMMU::Mode mode)
{
cpu->sendFetch(fault, req, tc);
}

15
src/cpu/translation.hh
View File

@@ -42,6 +42,7 @@
#ifndef __CPU_TRANSLATION_HH__
#define __CPU_TRANSLATION_HH__
#include "arch/generic/mmu.hh"
#include "arch/generic/tlb.hh"
#include "sim/faults.hh"
@@ -72,19 +73,19 @@ class WholeTranslationState
RequestPtr sreqHigh;
uint8_t *data;
uint64_t *res;
BaseTLB::Mode mode;
BaseMMU::Mode mode;
/**
* Single translation state. We set the number of outstanding
* translations to one and indicate that it is not split.
*/
WholeTranslationState(const RequestPtr &_req, uint8_t *_data,
uint64_t *_res, BaseTLB::Mode _mode)
uint64_t *_res, BaseMMU::Mode _mode)
: outstanding(1), delay(false), isSplit(false), mainReq(_req),
sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
{
faults[0] = faults[1] = NoFault;
assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
assert(mode == BaseMMU::Read || mode == BaseMMU::Write);
}
/**
@@ -94,13 +95,13 @@ class WholeTranslationState
*/
WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow,
const RequestPtr &_sreqHigh, uint8_t *_data,
uint64_t *_res, BaseTLB::Mode _mode)
uint64_t *_res, BaseMMU::Mode _mode)
: outstanding(2), delay(false), isSplit(true), mainReq(_req),
sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res),
mode(_mode)
{
faults[0] = faults[1] = NoFault;
assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
assert(mode == BaseMMU::Read || mode == BaseMMU::Write);
}
/**
@@ -215,7 +216,7 @@ class WholeTranslationState
* then the execution context is informed.
*/
template <class ExecContextPtr>
class DataTranslation : public BaseTLB::Translation
class DataTranslation : public BaseMMU::Translation
{
protected:
ExecContextPtr xc;
@@ -250,7 +251,7 @@ class DataTranslation : public BaseTLB::Translation
*/
void
finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
BaseTLB::Mode mode)
BaseMMU::Mode mode)
{
assert(state);
assert(mode == state->mode);