arch-riscv: CSR registers support in RISC-V remote GDB.

Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.

Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
	- struct r: added CSR registers
	- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
	- availableFeatures: indicate support for XML registers
	- getXferFeaturesRead: return XML blobs

Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38955
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/SConscript

@@ -3,6 +3,7 @@
 # Copyright (c) 2013 ARM Limited
 # Copyright (c) 2014 Sven Karlsson
 # Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -73,3 +74,8 @@ if env['TARGET_ISA'] == 'riscv':
 
     # Add in files generated by the ISA description.
     ISADesc('isa/main.isa')
+
+    GdbXml('riscv.xml', 'gdb_xml_riscv_target')
+    GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
+    GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
+    GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')