misc: Merge branch 'release-staging-v20.1.0.0' into develop

Change-Id: I3694b251855b969c7bd3807f34e1b4241d47d586

src/Doxyfile

@@ -31,7 +31,7 @@ PROJECT_NAME           = gem5
 # This could be handy for archiving the generated documentation or 
 # if some version control system is used.
 
-PROJECT_NUMBER         = DEVELOP-FOR-V20.1
+PROJECT_NUMBER         = v20.1.0.0
 
 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) 
 # base path where the generated documentation will be put. 

src/arch/arm/insts/tme64ruby.cc

@@ -109,15 +109,16 @@ Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
 
         // checkpointing occurs in the outer transaction only
         if (htm_depth == 1) {
-            auto new_cpt = new HTMCheckpoint();
+            BaseHTMCheckpointPtr& cpt = xc->tcBase()->getHtmCheckpointPtr();
 
-            new_cpt->save(tc);
-            new_cpt->destinationRegister(dest);
+            HTMCheckpoint *armcpt =
+                dynamic_cast<HTMCheckpoint*>(cpt.get());
+            assert(armcpt != nullptr);
+
+            armcpt->save(tc);
+            armcpt->destinationRegister(dest);
 
             ArmISA::globalClearExclusive(tc);
-
-            xc->tcBase()->setHtmCheckpointPtr(
-                std::unique_ptr<BaseHTMCheckpoint>(new_cpt));
         }
 
         xc->setIntRegOperand(this, 0, (Dest64) & mask(intWidth));

src/arch/arm/isa.cc

@@ -38,6 +38,7 @@
 #include "arch/arm/isa.hh"
 
 #include "arch/arm/faults.hh"
+#include "arch/arm/htm.hh"
 #include "arch/arm/interrupts.hh"
 #include "arch/arm/pmu.hh"
 #include "arch/arm/self_debug.hh"
@@ -439,9 +440,15 @@ ISA::startup()
 {
     BaseISA::startup();
 
-    if (tc)
+    if (tc) {
         setupThreadContext();
 
+        if (haveTME) {
+            std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
+            tc->setHtmCheckpointPtr(std::move(cpt));
+        }
+    }
+
     afterStartup = true;
 }
 

src/base/version.cc

@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "[DEVELOP-FOR-V20.1]";
+const char *gem5Version = "20.1.0.0";

src/cpu/o3/thread_context_impl.hh

@@ -347,7 +347,6 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
 {
-    assert(!thread->htmCheckpoint->valid());
     thread->htmCheckpoint = std::move(new_cpt);
 }
 

src/cpu/simple_thread.cc

@@ -196,6 +196,5 @@ SimpleThread::getHtmCheckpointPtr()
 void
 SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
 {
-    assert(!_htmCheckpoint->valid());
     _htmCheckpoint = std::move(new_cpt);
 }

src/mem/abstract_mem.cc

@@ -92,7 +92,8 @@ AbstractMemory::initState()
     panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
              name(), file);
 
-    PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); }, size());
+    PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
+                    system()->cacheLineSize());
 
     panic_if(!image.write(proxy), "%s: Unable to write image.");
 }

src/mem/ruby/common/BoolVec.cc

@@ -41,8 +41,8 @@
 #include <vector>
 
 std::ostream& operator<<(std::ostream& os, const BoolVec& myvector) {
-    for (const auto& it: myvector) {
-        os << " " << it;
+    for (const bool e: myvector) {
+        os << " " << e;
     }
     return os;
 }

src/mem/ruby/slicc_interface/RubySlicc_Util.hh

@@ -256,8 +256,8 @@ inline int
 countBoolVec(BoolVec bVec)
 {
     int count = 0;
-    for (const auto &it: bVec) {
-        if (it) {
+    for (const bool e: bVec) {
+        if (e) {
             count++;
         }
     }

src/mem/ruby/system/Sequencer.cc

@@ -167,7 +167,7 @@ Sequencer::wakeup()
     int total_outstanding = 0;
 
     for (const auto &table_entry : m_RequestTable) {
-        for (const auto seq_req : table_entry.second) {
+        for (const auto &seq_req : table_entry.second) {
             if (current_time - seq_req.issue_time < m_deadlock_threshold)
                 continue;
 

src/python/m5/simulate.py

@@ -175,7 +175,15 @@ def simulate(*args, **kwargs):
     if _drain_manager.isDrained():
         _drain_manager.resume()
 
-    return _m5.event.simulate(*args, **kwargs)
+    # We flush stdout and stderr before and after the simulation to ensure the
+    # output arrive in order.
+    sys.stdout.flush()
+    sys.stderr.flush()
+    sim_out = _m5.event.simulate(*args, **kwargs)
+    sys.stdout.flush()
+    sys.stderr.flush()
+
+    return sim_out
 
 def drain():
     """Drain the simulator in preparation of a checkpoint or memory mode

src/sim/pseudo_inst.cc

@@ -103,7 +103,7 @@ const std::string DIST_SIZE = "dist-size";
 static inline void
 panicFsOnlyPseudoInst(const char *name)
 {
-    panic("Pseudo inst \"%s\" is only available in Full System mode.");
+    panic("Pseudo inst \"%s\" is only available in Full System mode.", name);
 }
 
 void