From d031244ca70d86e1fa44d8d92c0dd4701a9a3db3 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 15 Jan 2024 11:48:51 +0000 Subject: [PATCH] misc: When unused, set #MatRegClass registers to 0 This is working around an existing SMT issue [1]. The BaseO3CPU uses two physical matrix registers [2]. This is enough for a single threaded CPU which as of now uses 1 architectural matrix only. The problem arises when SMT is enabled. As 2 architectural matrices need to be supported by a single CPU, the O3CPU won't have any available register in the freeList for renaming. This causes the SMT O3CPU to indefinitely stall renaming [3] If the archtectural number of registers is seto to 0, the regclass won't be taken into consideration when evaluating if we can rename instructions. This issue has been implicitly fixed for RISCV by a preceding PR [4] [1]: https://github.com/gem5/gem5/issues/668 [2]: https://github.com/gem5/gem5/blob/stable/src/cpu/o3/BaseO3CPU.py#L170 [3]: https://github.com/gem5/gem5/blob/stable/src/cpu/o3/rename.cc#L1228 [4]: https://github.com/gem5/gem5/pull/83 Change-Id: I99bfdefff11a246b1f191251dc67689e95b3f0db Signed-off-by: Giacomo Travaglini --- src/arch/mips/isa.cc | 2 +- src/arch/power/isa.cc | 2 +- src/arch/sparc/isa.cc | 2 +- src/arch/x86/isa.cc | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 92799ab291..7795456f15 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -105,7 +105,7 @@ constexpr RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); constexpr RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, debug::IntRegs); -constexpr RegClass matRegClass(MatRegClass, MatRegClassName, 1, debug::MatRegs); +constexpr RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs); constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc index ecaebade9a..50fbfd346d 100644 --- a/src/arch/power/isa.cc +++ b/src/arch/power/isa.cc @@ -57,7 +57,7 @@ RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, debug::IntRegs); -RegClass matRegClass(MatRegClass, MatRegClassName, 1, debug::MatRegs); +RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs); RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index e7807c2b0a..9bb169aefe 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -74,7 +74,7 @@ RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, debug::IntRegs); -RegClass matRegClass(MatRegClass, MatRegClassName, 1, debug::MatRegs); +RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs); RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 7d401a6c59..dd49326a4f 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -147,7 +147,7 @@ RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, debug::IntRegs); -RegClass matRegClass(MatRegClass, MatRegClassName, 1, debug::MatRegs); +RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs); } // anonymous namespace