From d023d8a3dd49726e3dbd44f9267ef8832b825692 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Wed, 10 Aug 2022 14:20:01 -0700 Subject: [PATCH] stdlib: Remove "CPUType" from AbstractCore This constraint bound us in many ways. There are many cases where we want a core in a component which does not correspond to a CPUType enum value. This refactoring makes it so only SimpleCore utilizes this. Docstrings have been updated to reflect this change. Change-Id: I918c73310fc530dd060691cf9be65163cacfffb4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62291 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- .../gem5/components/processors/abstract_core.py | 12 +++--------- .../processors/abstract_generator_core.py | 8 +++----- .../gem5/components/processors/simple_core.py | 16 +++++++++++++++- .../components/processors/simple_processor.py | 6 +++--- .../processors/switchable_processor.py | 2 +- 5 files changed, 25 insertions(+), 19 deletions(-) diff --git a/src/python/gem5/components/processors/abstract_core.py b/src/python/gem5/components/processors/abstract_core.py index 9045369491..73cc400eb2 100644 --- a/src/python/gem5/components/processors/abstract_core.py +++ b/src/python/gem5/components/processors/abstract_core.py @@ -39,14 +39,8 @@ from m5.objects import BaseMMU, Port, SubSystem class AbstractCore(SubSystem): __metaclass__ = ABCMeta - def __init__(self, cpu_type: CPUTypes): + def __init__(self): super().__init__() - if cpu_type == CPUTypes.KVM: - requires(kvm_required=True) - self._cpu_type = cpu_type - - def get_type(self) -> CPUTypes: - return self._cpu_type @abstractmethod def get_isa(self) -> ISA: @@ -97,7 +91,7 @@ class AbstractCore(SubSystem): interrupt_requestor: Optional[Port] = None, interrupt_responce: Optional[Port] = None, ) -> None: - """ Connect the core interrupts to the interrupt controller + """Connect the core interrupts to the interrupt controller This function is usually called from the cache hierarchy since the optional ports can be implemented as cache ports. @@ -106,7 +100,7 @@ class AbstractCore(SubSystem): @abstractmethod def get_mmu(self) -> BaseMMU: - """ Return the MMU for this core. + """Return the MMU for this core. This is used in the board to setup system-specific MMU settings. """ diff --git a/src/python/gem5/components/processors/abstract_generator_core.py b/src/python/gem5/components/processors/abstract_generator_core.py index 48a4e818f0..97ea36cbb3 100644 --- a/src/python/gem5/components/processors/abstract_generator_core.py +++ b/src/python/gem5/components/processors/abstract_generator_core.py @@ -48,12 +48,10 @@ class AbstractGeneratorCore(AbstractCore): def __init__(self): """ - Create an AbstractCore with the CPUType of Timing. Also, setup a - dummy generator object to connect to icache + Create an AbstractCore. Also, setup a dummy generator object to connect + to icache. """ - # TODO: Remove the CPU Type parameter. This not needed. - # Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031 - super().__init__(CPUTypes.TIMING) + super().__init__() self.port_end = PortTerminator() @overrides(AbstractCore) diff --git a/src/python/gem5/components/processors/simple_core.py b/src/python/gem5/components/processors/simple_core.py index 7e3c8611d5..c285fe7d98 100644 --- a/src/python/gem5/components/processors/simple_core.py +++ b/src/python/gem5/components/processors/simple_core.py @@ -32,15 +32,26 @@ from .cpu_types import CPUTypes from ...isas import ISA from ...runtime import get_runtime_isa from ...utils.override import overrides +from ...utils.requires import requires from m5.objects import BaseMMU, Port, BaseCPU, Process class SimpleCore(AbstractCore): + """ + A SimpleCore instantiates a core based on the CPUType enum pass. The + SimpleCore creates a single SimObject of that type. + """ + def __init__( self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None ): - super().__init__(cpu_type=cpu_type) + super().__init__() + + self._cpu_type = cpu_type + if cpu_type == CPUTypes.KVM: + requires(kvm_required=True) + if isa: requires(isa_required=isa) self._isa = isa @@ -54,6 +65,9 @@ class SimpleCore(AbstractCore): def get_simobject(self) -> BaseCPU: return self.core + def get_type(self) -> CPUTypes: + return self._cpu_type + @overrides(AbstractCore) def get_isa(self) -> ISA: return self._isa diff --git a/src/python/gem5/components/processors/simple_processor.py b/src/python/gem5/components/processors/simple_processor.py index 2fa206f41f..c759625206 100644 --- a/src/python/gem5/components/processors/simple_processor.py +++ b/src/python/gem5/components/processors/simple_processor.py @@ -41,15 +41,15 @@ from typing import Optional class SimpleProcessor(AbstractProcessor): """ - A SimpeProcessor contains a number of cores of a a single CPUType. + A SimpleProcessor contains a number of cores of SimpleCore objects of the + same CPUType. """ def __init__( self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] = None ) -> None: """ - param cpu_type: The CPU type for each type in the processor. -: + :param cpu_type: The CPU type for each type in the processor. :param num_cores: The number of CPU cores in the processor. :param isa: The ISA of the processor. This argument is optional. If not diff --git a/src/python/gem5/components/processors/switchable_processor.py b/src/python/gem5/components/processors/switchable_processor.py index 8432f5d77c..abf7f1e22f 100644 --- a/src/python/gem5/components/processors/switchable_processor.py +++ b/src/python/gem5/components/processors/switchable_processor.py @@ -41,7 +41,7 @@ from ...utils.override import * class SwitchableProcessor(AbstractProcessor): """ This class can be used to setup a switchable processor/processors on a - system. + system using SimpleCores. Though this class can be used directly, it is best inherited from. See "SimpleSwitchableCPU" for an example of this.