From a47ca9dadcf2fec62d20097fad1a80fca7fd927d Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:29:01 -0700 Subject: [PATCH 1/4] arch-riscv: Add a function generating the ISA string Currently, we are hardcoding the ISA string in the device tree generator. The ISA string from the device tree affects which ISA extensions will be used by the bootloader/kernel. This function allows generating the ISA string from the gem5's ISA object rather than using hardcoded values. Change-Id: I2f3720fb6da24347f38f26d9a49939484b11d3bb Signed-off-by: Hoa Nguyen --- src/arch/riscv/RiscvISA.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py index 3f123405e9..62dcffb5d8 100644 --- a/src/arch/riscv/RiscvISA.py +++ b/src/arch/riscv/RiscvISA.py @@ -13,6 +13,7 @@ # # Copyright (c) 2016 RISC-V Foundation # Copyright (c) 2016 The University of Virginia +# Copyright (c) 2023 The Regents of the University of California # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -94,3 +95,18 @@ class RiscvISA(BaseISA): "Length of each vector element in bits. \ ELEN in Ch. 2 of RISC-V vector spec", ) + + def get_isa_string(self): + isa_extensions = [] + # check for the base ISA type + if self.riscv_type.value == "RV32": + isa_extensions.append("rv32") + elif self.riscv_type.value == "RV64": + isa_extensions.append("rv64") + # use imafdc by default + isa_extensions.extend(["i", "m", "a", "f", "d", "c"]) + # check for the vector extension + if self.enable_rvv.value == True: + isa_extensions.append("v") + isa_string = "".join(isa_extensions) + return isa_string From 4f72f6172ac6e44b770a590a5cfbab063ce36412 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:36:20 -0700 Subject: [PATCH 2/4] stdlib: Use the ISA string generator in the RiscvBoard Current hardcoded value does not support vector instructions. The new ISA string generator function allows the flexibility of using or not using the vector extension. Change-Id: Ic78c4b6629ad3813fc172f700d77ea956552e613 Signed-off-by: Hoa Nguyen --- src/python/gem5/components/boards/riscv_board.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index 450fcb7866..9b0d6454e1 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -280,7 +280,11 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload): node.append(FdtPropertyWords("reg", state.CPUAddrCells(i))) node.append(FdtPropertyStrings("mmu-type", "riscv,sv48")) node.append(FdtPropertyStrings("status", "okay")) - node.append(FdtPropertyStrings("riscv,isa", "rv64imafdc")) + node.append( + FdtPropertyStrings( + "riscv,isa", core.core.isa[0].get_isa_string() + ) + ) # TODO: Should probably get this from the core. freq = self.clk_domain.clock[0].frequency node.append(FdtPropertyWords("clock-frequency", freq)) From dce8d07703d0a799959b7bce79c43790775b0323 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:42:35 -0700 Subject: [PATCH 3/4] stdlib: Turn off RVV for U74 core The U74 core doesn't support vector instructions. Change-Id: Iadfb6b43ef8c62dcad23391e468a43b908e4a22c Signed-off-by: Hoa Nguyen --- src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py index 22ec29e59d..19dc2f2e8c 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py @@ -214,3 +214,4 @@ class U74Core(BaseCPUCore): core_id, ): super().__init__(core=U74CPU(cpu_id=core_id), isa=ISA.RISCV) + self.core.isa[0].enable_rvv = False From 50196863a4148d50421b6228bf0b8362d811d0eb Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:54:22 -0700 Subject: [PATCH 4/4] stdlib,dev: Fix several hardcoded RISC-V ISA strings The "s" and "u" letters are not recognized by the Linux kernel as RISC-V extensions [1]. [1] https://elixir.bootlin.com/linux/v6.5.7/source/arch/riscv/kernel/cpufeature.c#L170 Change-Id: I2a99557482cde6e6d6160626b3995275c41b1577 Signed-off-by: Hoa Nguyen --- src/dev/riscv/HiFive.py | 2 +- src/python/gem5/components/boards/experimental/lupv_board.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py index 5bd6363363..c3d51aa5e7 100755 --- a/src/dev/riscv/HiFive.py +++ b/src/dev/riscv/HiFive.py @@ -251,7 +251,7 @@ class HiFive(HiFiveBase): def annotateCpuDeviceNode(self, cpu, state): cpu.append(FdtPropertyStrings("mmu-type", "riscv,sv48")) cpu.append(FdtPropertyStrings("status", "okay")) - cpu.append(FdtPropertyStrings("riscv,isa", "rv64imafdcsu")) + cpu.append(FdtPropertyStrings("riscv,isa", "rv64imafdc")) cpu.appendCompatible(["riscv"]) int_node = FdtNode("interrupt-controller") diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py b/src/python/gem5/components/boards/experimental/lupv_board.py index a0ec89eafb..85843b89e2 100644 --- a/src/python/gem5/components/boards/experimental/lupv_board.py +++ b/src/python/gem5/components/boards/experimental/lupv_board.py @@ -316,7 +316,7 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload): node.append(FdtPropertyWords("reg", state.CPUAddrCells(i))) node.append(FdtPropertyStrings("mmu-type", "riscv,sv48")) node.append(FdtPropertyStrings("status", "okay")) - node.append(FdtPropertyStrings("riscv,isa", "rv64imafdcsu")) + node.append(FdtPropertyStrings("riscv,isa", "rv64imafdc")) # TODO: Should probably get this from the core. freq = self.clk_domain.clock[0].frequency node.appendCompatible(["riscv"])