From 752b937ff73f52cd3580ac15d21f350718eabde3 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 14 Mar 2005 17:58:02 -0500 Subject: [PATCH 01/19] helpful DPRINTF changes - more info is good! --HG-- extra : convert_revision : a2d820bb97cab2c635a7192562daedd8d7784ec8 From 2ba8bc81847a662ce1d5553a5d5207ed9c50e361 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 15 Mar 2005 11:28:24 -0500 Subject: [PATCH 02/19] fetch.cc: undo ron's fix that i checked in, it caused the deadlock. --HG-- extra : convert_revision : dab85d748ba651d3c2debdd6577c53b998f0d96e From caf16a99cc70bd9cf4078a7e08d208984a116951 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 Mar 2005 17:31:18 -0500 Subject: [PATCH 03/19] during a cache miss in the simple cpu we were finalizing the trace data too early (before the cache miss completed) and therefore writing freeded memory after the cache miss completed. Also removed some spurious setAddr() and setData() calls. --HG-- extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2 --- cpu/simple_cpu/simple_cpu.cc | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 86aeab7d71..6a95a52c2c 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -393,13 +393,11 @@ template Fault SimpleCPU::read(Addr addr, T &data, unsigned flags) { - if (status() == DcacheMissStall) { + if (status() == DcacheMissStall || status() == DcacheMissSwitch) { Fault fault = xc->read(memReq,data); if (traceData) { traceData->setAddr(addr); - if (fault == No_Fault) - traceData->setData(data); } return fault; } @@ -428,21 +426,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) // do functional access fault = xc->read(memReq, data); - if (traceData) { - traceData->setAddr(addr); - if (fault == No_Fault) - traceData->setData(data); - } } } else if(fault == No_Fault) { // do functional access fault = xc->read(memReq, data); - if (traceData) { - traceData->setAddr(addr); - if (fault == No_Fault) - traceData->setData(data); - } } if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) @@ -498,11 +486,6 @@ template Fault SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { - if (traceData) { - traceData->setAddr(addr); - traceData->setData(data); - } - memReq->reset(addr, sizeof(T), flags); // translate to physical address @@ -605,6 +588,8 @@ SimpleCPU::processCacheCompletion() case DcacheMissStall: if (memReq->cmd.isRead()) { curStaticInst->execute(this,traceData); + if (traceData) + traceData->finalize(); } dcacheStallCycles += curTick - lastDcacheStall; _status = Running; @@ -613,6 +598,8 @@ SimpleCPU::processCacheCompletion() case DcacheMissSwitch: if (memReq->cmd.isRead()) { curStaticInst->execute(this,traceData); + if (traceData) + traceData->finalize(); } _status = SwitchedOut; sampler->signalSwitched(); @@ -785,8 +772,12 @@ SimpleCPU::tick() comLoadEventQueue[0]->serviceEvents(numLoad); } - if (traceData) + // If we have a dcache miss, then we can't finialize the instruction + // trace yet because we want to populate it with the data later + if (traceData && + !(status() == DcacheMissStall && memReq->cmd.isRead())) { traceData->finalize(); + } traceFunctions(xc->regs.pc); From 6aaa9a7d63d4a11746ebd11332355a80d031dbb0 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 Mar 2005 18:07:46 -0500 Subject: [PATCH 04/19] only increment invalid address loads on misspeculated instructions --HG-- extra : convert_revision : b68f730a1ea43c75ea1596c4219f66c0fce9dd0a From 42753edb3c93cbc2ef7a6698b88b20bd641122fe Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 15 Mar 2005 19:41:51 -0500 Subject: [PATCH 05/19] Add a comment to smartdict.py. python/m5/smartdict.py: Add a comment explaining why this actually works. --HG-- extra : convert_revision : 39cbde547f4bf6cf626ab1c0b6ef56a5788b09b8 --- python/m5/smartdict.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/python/m5/smartdict.py b/python/m5/smartdict.py index 4ea8210d36..1ba5d8410b 100644 --- a/python/m5/smartdict.py +++ b/python/m5/smartdict.py @@ -74,6 +74,12 @@ class SmartDict(dict): return other / self.convert(other) + # __getitem__ uses dict.get() to return 'False' if the key is not + # found (rather than raising KeyError). Note that this does *not* + # set the key's value to 'False' in the dict, so that even after + # we call env['foo'] we still get a meaningful answer from "'foo' + # in env" (which calls dict.__contains__, which we do not + # override). def __getitem__(self, key): return self.Proxy(dict.get(self, key, 'False')) From c8538d6a7e2b58ebcbe567023c9e1c5a0c3ee5a6 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Mar 2005 00:40:48 -0500 Subject: [PATCH 06/19] Enhancements to python config proxy class. python/m5/config.py: - Enhanced Proxy class now supports subscripting, e.g., parent.cpu[0] or even parent.cpu[0].icache. - Proxy also supports multiplication (e.g., parent.cycle * 3), though this feature has not been tested. - Subscript 0 works even on non-lists, so you can safely say cpu[0] and get the first cpu even if there's only one. - Changed name of proxy object from 'Super' to 'parent', and changed "wild card" notation from plain 'Super' to 'parent.any'. python/m5/objects/AlphaConsole.mpy: python/m5/objects/BaseCPU.mpy: python/m5/objects/BaseSystem.mpy: python/m5/objects/Device.mpy: python/m5/objects/Ethernet.mpy: python/m5/objects/Ide.mpy: python/m5/objects/IntrControl.mpy: python/m5/objects/Pci.mpy: python/m5/objects/PhysicalMemory.mpy: python/m5/objects/Platform.mpy: python/m5/objects/SimConsole.mpy: python/m5/objects/SimpleDisk.mpy: python/m5/objects/Tsunami.mpy: python/m5/objects/Uart.mpy: Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any'). --HG-- extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d --- python/m5/config.py | 133 +++++++++++++++++++-------- python/m5/objects/AlphaConsole.mpy | 6 +- python/m5/objects/BaseCPU.mpy | 2 +- python/m5/objects/BaseSystem.mpy | 4 +- python/m5/objects/Device.mpy | 4 +- python/m5/objects/Ethernet.mpy | 6 +- python/m5/objects/Ide.mpy | 2 +- python/m5/objects/IntrControl.mpy | 2 +- python/m5/objects/Pci.mpy | 4 +- python/m5/objects/PhysicalMemory.mpy | 2 +- python/m5/objects/Platform.mpy | 2 +- python/m5/objects/SimConsole.mpy | 2 +- python/m5/objects/SimpleDisk.mpy | 2 +- python/m5/objects/Tsunami.mpy | 8 +- python/m5/objects/Uart.mpy | 2 +- 15 files changed, 118 insertions(+), 63 deletions(-) diff --git a/python/m5/config.py b/python/m5/config.py index 182acf393e..e6ad5a0ba5 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -139,25 +139,90 @@ class Singleton(type): ##################################################################### class Proxy(object): - def __init__(self, path = ()): + def __init__(self, path): self._object = None - self._path = path + if path == 'any': + self._path = None + else: + # path is a list of (attr,index) tuples + self._path = [(path,None)] + self._index = None + self._multiplier = None def __getattr__(self, attr): - return Proxy(self._path + (attr, )) + if attr == '__bases__': + return super(Proxy, self).__getattr__(self, attr) + self._path.append((attr,None)) + return self def __setattr__(self, attr, value): if not attr.startswith('_'): raise AttributeError, 'cannot set attribute %s' % attr super(Proxy, self).__setattr__(attr, value) - def _convert(self): - obj = self._object - for attr in self._path: - obj = obj.__getattribute__(attr) - return obj + # support indexing on proxies (e.g., parent.cpu[0]) + def __getitem__(self, key): + if not isinstance(key, int): + raise TypeError, "Proxy object requires integer index" + if self._path == None: + raise IndexError, "Index applied to 'any' proxy" + # replace index portion of last path element with new index + self._path[-1] = (self._path[-1][0], key) + return self -Super = Proxy() + # support multiplying proxies by constants + def __mul__(self, other): + if not isinstance(other, int): + raise TypeError, "Proxy multiplier must be integer" + if self._multiplier == None: + self._multiplier = other + else: + # support chained multipliers + self._multiplier *= other + return self + + def _mulcheck(self, result): + if self._multiplier == None: + return result + if not isinstance(result, int): + raise TypeError, "Proxy with multiplier resolves to " \ + "non-integer value" + return result * self._multiplier + + def unproxy(self, base, ptype): + obj = base + done = False + while not done: + if obj is None: + raise AttributeError, \ + 'Parent of %s type %s not found at path %s' \ + % (base.name, ptype, self._path) + found, done = obj.find(ptype, self._path) + if isinstance(found, Proxy): + done = False + obj = obj.parent + + return self._mulcheck(found) + + def getindex(obj, index): + if index == None: + return obj + try: + obj = obj[index] + except TypeError: + if index != 0: + raise + # if index is 0 and item is not subscriptable, just + # use item itself (so cpu[0] works on uniprocessors) + return obj + getindex = staticmethod(getindex) + +class ProxyFactory(object): + def __getattr__(self, attr): + return Proxy(attr) + +# global object for handling parent.foo proxies +parent = ProxyFactory() def isSubClass(value, cls): try: @@ -643,50 +708,40 @@ class Node(object): if issubclass(child.realtype, realtype): if obj is not None: raise AttributeError, \ - 'Super matched more than one: %s %s' % \ + 'parent.any matched more than one: %s %s' % \ (obj.path, child.path) obj = child return obj, obj is not None try: obj = self - for node in path[:-1]: - obj = obj.child_names[node] + for (node,index) in path[:-1]: + if obj.child_names.has_key(node): + obj = obj.child_names[node] + else: + obj = obj.top_child_names[node] + obj = Proxy.getindex(obj, index) - last = path[-1] + (last,index) = path[-1] if obj.child_names.has_key(last): value = obj.child_names[last] - if issubclass(value.realtype, realtype): - return value, True + return Proxy.getindex(value, index), True + elif obj.top_child_names.has_key(last): + value = obj.top_child_names[last] + return Proxy.getindex(value, index), True elif obj.param_names.has_key(last): value = obj.param_names[last] realtype._convert(value.value) - return value.value, True + return Proxy.getindex(value.value, index), True except KeyError: pass return None, False - def unproxy(self, ptype, value): - if not isinstance(value, Proxy): - return value - - if value is None: - raise AttributeError, 'Error while fixing up %s' % self.path - - obj = self - done = False - while not done: - if obj is None: - raise AttributeError, \ - 'Parent of %s type %s not found at path %s' \ - % (self.name, ptype, value._path) - found, done = obj.find(ptype, value._path) - if isinstance(found, Proxy): - done = False - obj = obj.parent - - return found + def unproxy(self, param, ptype): + if not isinstance(param, Proxy): + return param + return param.unproxy(self, ptype) def fixup(self): self.all[self.path] = self @@ -697,9 +752,9 @@ class Node(object): try: if isinstance(pval, (list, tuple)): - param.value = [ self.unproxy(ptype, pv) for pv in pval ] + param.value = [ self.unproxy(pv, ptype) for pv in pval ] else: - param.value = self.unproxy(ptype, pval) + param.value = self.unproxy(pval, ptype) except: print 'Error while fixing up %s:%s' % (self.path, param.name) raise @@ -1337,7 +1392,7 @@ class SimObject(ConfigNode, ParamType): # 'from config import *' is invoked. Try to keep this reasonably # short to avoid polluting other namespaces. __all__ = ['ConfigNode', 'SimObject', 'ParamContext', 'Param', 'VectorParam', - 'Super', 'Enum', + 'parent', 'Enum', 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16', 'Int32', 'UInt32', 'Int64', 'UInt64', 'Counter', 'Addr', 'Tick', 'Percent', diff --git a/python/m5/objects/AlphaConsole.mpy b/python/m5/objects/AlphaConsole.mpy index 79918a01e2..63aea5b7d6 100644 --- a/python/m5/objects/AlphaConsole.mpy +++ b/python/m5/objects/AlphaConsole.mpy @@ -2,8 +2,8 @@ from Device import PioDevice simobj AlphaConsole(PioDevice): type = 'AlphaConsole' - cpu = Param.BaseCPU(Super, "Processor") + cpu = Param.BaseCPU(parent.any, "Processor") disk = Param.SimpleDisk("Simple Disk") num_cpus = Param.Int(1, "Number of CPUs") - sim_console = Param.SimConsole(Super, "The Simulator Console") - system = Param.BaseSystem(Super, "system object") + sim_console = Param.SimConsole(parent.any, "The Simulator Console") + system = Param.BaseSystem(parent.any, "system object") diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy index 5d8305d888..d84e30e534 100644 --- a/python/m5/objects/BaseCPU.mpy +++ b/python/m5/objects/BaseCPU.mpy @@ -8,7 +8,7 @@ simobj BaseCPU(SimObject): dtb = Param.AlphaDTB("Data TLB") itb = Param.AlphaITB("Instruction TLB") mem = Param.FunctionalMemory("memory") - system = Param.BaseSystem(Super, "system object") + system = Param.BaseSystem(parent.any, "system object") else: workload = VectorParam.Process("processes to run") diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.mpy index 1cbdf4e99a..450b6a58e1 100644 --- a/python/m5/objects/BaseSystem.mpy +++ b/python/m5/objects/BaseSystem.mpy @@ -1,8 +1,8 @@ simobj BaseSystem(SimObject): type = 'BaseSystem' abstract = True - memctrl = Param.MemoryController(Super, "memory controller") - physmem = Param.PhysicalMemory(Super, "phsyical memory") + memctrl = Param.MemoryController(parent.any, "memory controller") + physmem = Param.PhysicalMemory(parent.any, "phsyical memory") kernel = Param.String("file that contains the kernel code") console = Param.String("file that contains the console code") pal = Param.String("file that contains palcode") diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.mpy index 47f8db1cbe..a0d02a6473 100644 --- a/python/m5/objects/Device.mpy +++ b/python/m5/objects/Device.mpy @@ -14,7 +14,7 @@ simobj FooPioDevice(FunctionalMemory): type = 'PioDevice' abstract = True addr = Param.Addr("Device Address") - mmu = Param.MemoryController(Super, "Memory Controller") + mmu = Param.MemoryController(parent.any, "Memory Controller") io_bus = Param.Bus(NULL, "The IO Bus to attach to") pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") @@ -25,7 +25,7 @@ simobj FooDmaDevice(FooPioDevice): simobj PioDevice(FooPioDevice): type = 'PioDevice' abstract = True - platform = Param.Platform(Super, "Platform") + platform = Param.Platform(parent.any, "Platform") simobj DmaDevice(PioDevice): type = 'DmaDevice' diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy index 088df4b932..cd251f36da 100644 --- a/python/m5/objects/Ethernet.mpy +++ b/python/m5/objects/Ethernet.mpy @@ -49,8 +49,8 @@ simobj EtherDev(DmaDevice): intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Super, "Physical Memory") - tlaser = Param.Turbolaser(Super, "Turbolaser") + physmem = Param.PhysicalMemory(parent.any, "Physical Memory") + tlaser = Param.Turbolaser(parent.any, "Turbolaser") simobj NSGigE(PciDevice): type = 'NSGigE' @@ -73,7 +73,7 @@ simobj NSGigE(PciDevice): intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Super, "Physical Memory") + physmem = Param.PhysicalMemory(parent.any, "Physical Memory") simobj EtherDevInt(EtherInt): type = 'EtherDevInt' diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.mpy index ce760ad96b..786109efa4 100644 --- a/python/m5/objects/Ide.mpy +++ b/python/m5/objects/Ide.mpy @@ -7,7 +7,7 @@ simobj IdeDisk(SimObject): delay = Param.Tick(1, "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") - physmem = Param.PhysicalMemory(Super, "Physical memory") + physmem = Param.PhysicalMemory(parent.any, "Physical memory") simobj IdeController(PciDevice): type = 'IdeController' diff --git a/python/m5/objects/IntrControl.mpy b/python/m5/objects/IntrControl.mpy index 1ef5a17ee3..144be0fd46 100644 --- a/python/m5/objects/IntrControl.mpy +++ b/python/m5/objects/IntrControl.mpy @@ -1,3 +1,3 @@ simobj IntrControl(SimObject): type = 'IntrControl' - cpu = Param.BaseCPU(Super, "the cpu") + cpu = Param.BaseCPU(parent.any, "the cpu") diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.mpy index f7c6674f74..b9b3e5a956 100644 --- a/python/m5/objects/Pci.mpy +++ b/python/m5/objects/Pci.mpy @@ -47,5 +47,5 @@ simobj PciDevice(DmaDevice): pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") pci_func = Param.Int("PCI function code") - configdata = Param.PciConfigData(Super, "PCI Config data") - configspace = Param.PciConfigAll(Super, "PCI Configspace") + configdata = Param.PciConfigData(parent.any, "PCI Config data") + configspace = Param.PciConfigAll(parent.any, "PCI Configspace") diff --git a/python/m5/objects/PhysicalMemory.mpy b/python/m5/objects/PhysicalMemory.mpy index d1e4ad4b40..e6df2a1614 100644 --- a/python/m5/objects/PhysicalMemory.mpy +++ b/python/m5/objects/PhysicalMemory.mpy @@ -4,4 +4,4 @@ simobj PhysicalMemory(FunctionalMemory): type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") - mmu = Param.MemoryController(Super, "Memory Controller") + mmu = Param.MemoryController(parent.any, "Memory Controller") diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy index d0510eaf87..a71ab3b770 100644 --- a/python/m5/objects/Platform.mpy +++ b/python/m5/objects/Platform.mpy @@ -2,4 +2,4 @@ simobj Platform(SimObject): type = 'Platform' abstract = True interrupt_frequency = Param.Tick(1200, "frequency of interrupts") - intrctrl = Param.IntrControl(Super, "interrupt controller") + intrctrl = Param.IntrControl(parent.any, "interrupt controller") diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy index fb74f17750..3588a949d8 100644 --- a/python/m5/objects/SimConsole.mpy +++ b/python/m5/objects/SimConsole.mpy @@ -5,7 +5,7 @@ simobj ConsoleListener(SimObject): simobj SimConsole(SimObject): type = 'SimConsole' append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Super, "interrupt controller") + intr_control = Param.IntrControl(parent.any, "interrupt controller") listener = Param.ConsoleListener("console listener") number = Param.Int(0, "console number") output = Param.String('console', "file to dump output to") diff --git a/python/m5/objects/SimpleDisk.mpy b/python/m5/objects/SimpleDisk.mpy index c4dd5435bf..b616fb3d12 100644 --- a/python/m5/objects/SimpleDisk.mpy +++ b/python/m5/objects/SimpleDisk.mpy @@ -1,4 +1,4 @@ simobj SimpleDisk(SimObject): type = 'SimpleDisk' disk = Param.DiskImage("Disk Image") - physmem = Param.PhysicalMemory(Super, "Physical Memory") + physmem = Param.PhysicalMemory(parent.any, "Physical Memory") diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.mpy index cfe23977e0..a8471cee23 100644 --- a/python/m5/objects/Tsunami.mpy +++ b/python/m5/objects/Tsunami.mpy @@ -4,12 +4,12 @@ from Platform import Platform simobj Tsunami(Platform): type = 'Tsunami' pciconfig = Param.PciConfigAll("PCI configuration") - system = Param.BaseSystem(Super, "system") + system = Param.BaseSystem(parent.any, "system") interrupt_frequency = Param.Int(1024, "frequency of interrupts") simobj TsunamiCChip(FooPioDevice): type = 'TsunamiCChip' - tsunami = Param.Tsunami(Super, "Tsunami") + tsunami = Param.Tsunami(parent.any, "Tsunami") simobj TsunamiFake(FooPioDevice): type = 'TsunamiFake' @@ -18,8 +18,8 @@ simobj TsunamiIO(FooPioDevice): type = 'TsunamiIO' time = Param.UInt64(1136073600, "System time to use (0 for actual time, default is 1/1/06)") - tsunami = Param.Tsunami(Super, "Tsunami") + tsunami = Param.Tsunami(parent.any, "Tsunami") simobj TsunamiPChip(FooPioDevice): type = 'TsunamiPChip' - tsunami = Param.Tsunami(Super, "Tsunami") + tsunami = Param.Tsunami(parent.any, "Tsunami") diff --git a/python/m5/objects/Uart.mpy b/python/m5/objects/Uart.mpy index 76ee8805f8..5a6c25f8ec 100644 --- a/python/m5/objects/Uart.mpy +++ b/python/m5/objects/Uart.mpy @@ -2,5 +2,5 @@ from Device import PioDevice simobj Uart(PioDevice): type = 'Uart' - console = Param.SimConsole(Super, "The console") + console = Param.SimConsole(parent.any, "The console") size = Param.Addr(0x8, "Device size") From df012f26fa9797896e3f571c81d336bec0a97b98 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 10:30:33 -0500 Subject: [PATCH 07/19] Fix the bad addr check to check for allowable addresses in the nxm address space arch/alpha/alpha_tru64_process.cc: sim/process.cc: sim/process.hh: Add an address range for the nxm sim/syscall_emul.hh: Check to make sure that if we have an nxm config space that the mmap hasn't grown into it --HG-- extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77 --- arch/alpha/alpha_tru64_process.cc | 4 ++++ sim/process.cc | 1 + sim/process.hh | 11 ++++++++++- sim/syscall_emul.hh | 4 ++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc index 22e74cb40c..8660cc5c5c 100644 --- a/arch/alpha/alpha_tru64_process.cc +++ b/arch/alpha/alpha_tru64_process.cc @@ -877,6 +877,10 @@ class Tru64 { *configptr_ptr = config_addr; configptr_ptr.copyOut(xc->mem); + // Register this as a valid address range with the process + process->nxm_start = base_addr; + process->nxm_end = cur_addr; + return 0; } diff --git a/sim/process.cc b/sim/process.cc index 7111e87337..c18b31da76 100644 --- a/sim/process.cc +++ b/sim/process.cc @@ -89,6 +89,7 @@ Process::Process(const string &nm, } mmap_start = mmap_end = 0; + nxm_start = nxm_end = 0; // other parameters will be initialized when the program is loaded } diff --git a/sim/process.hh b/sim/process.hh index 1ab43cd62b..1c6c6b3fb1 100644 --- a/sim/process.hh +++ b/sim/process.hh @@ -97,6 +97,10 @@ class Process : public SimObject Addr mmap_start; Addr mmap_end; + // Base of region for nxm data + Addr nxm_start; + Addr nxm_end; + std::string prog_fname; // file name Addr prog_entry; // entry point (initial PC) @@ -159,9 +163,14 @@ class Process : public SimObject bool validDataAddr(Addr addr) { return ((data_base <= addr && addr < brk_point) || +#ifdef FULLSYSTEM ((stack_base - 16*1024*1024) <= addr && addr < stack_base) || +#else + (next_thread_stack_base <= addr && addr < stack_base) || +#endif (text_base <= addr && addr < (text_base + text_size)) || - (mmap_start <= addr && addr < mmap_end)); + (mmap_start <= addr && addr < mmap_end) || + (nxm_start <= addr && addr < nxm_end)); } virtual void syscall(ExecContext *xc) = 0; diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh index 51a075a28f..69c17c3309 100644 --- a/sim/syscall_emul.hh +++ b/sim/syscall_emul.hh @@ -412,6 +412,10 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) // user didn't give an address... pick one from our "mmap region" start = p->mmap_end; p->mmap_end += RoundUp(length, VMPageSize); + if (p->nxm_start != 0) { + //If we have an nxm space, make sure we haven't colided + assert(p->mmap_end < p->nxm_start); + } } if (!(flags & OS::TGT_MAP_ANONYMOUS)) { From d80522183992207132e638ce2bb02513758bb61f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Mar 2005 10:39:02 -0500 Subject: [PATCH 08/19] Forgot to commit run.mpy with last changeset (really belongs there). --HG-- extra : convert_revision : 67055c33cc3b2b115595d3cd4a3df5356ca970f9 From d40a1c6573447bd01058611f88256ddc514439c3 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 16 Mar 2005 13:55:58 -0500 Subject: [PATCH 09/19] Some changes to NSGigE's DPRINTF's that helped when I was doing NAT stuff. --HG-- extra : convert_revision : d36c84a835667d4c67f46432a90b9557b0710eac --- dev/ns_gige.cc | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index db1474d1cc..53a881ef70 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -1597,8 +1597,10 @@ NSGigE::rxKick() DPRINTF(Ethernet, "ID is %d\n", ip->id()); TcpPtr tcp(ip); if (tcp) { - DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n", - tcp->sport(), tcp->dport()); + DPRINTF(Ethernet, + "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n", + tcp->sport(), tcp->dport(), tcp->seq(), + tcp->ack()); } } } @@ -1803,14 +1805,15 @@ NSGigE::transmit() DPRINTF(Ethernet, "ID is %d\n", ip->id()); TcpPtr tcp(ip); if (tcp) { - DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n", - tcp->sport(), tcp->dport()); + DPRINTF(Ethernet, + "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n", + tcp->sport(), tcp->dport(), tcp->seq(), tcp->ack()); } } } #endif - DDUMP(Ethernet, txFifo.front()->data, txFifo.front()->length); + DDUMP(EthernetData, txFifo.front()->data, txFifo.front()->length); txBytes += txFifo.front()->length; txPackets++; @@ -2296,8 +2299,18 @@ NSGigE::recvPacket(PacketPtr packet) } if (rxFifo.avail() < packet->length) { - DPRINTF(Ethernet, - "packet will not fit in receive buffer...packet dropped\n"); +#if TRACING_ON + IpPtr ip(packet); + TcpPtr tcp(ip); + if (ip) { + DPRINTF(Ethernet, + "packet won't fit in receive buffer...pkt ID %d dropped\n", + ip->id()); + if (tcp) { + DPRINTF(Ethernet, "Seq=%d\n", tcp->seq()); + } + } +#endif droppedPackets++; devIntrPost(ISR_RXORN); return false; From b411e0d4ac8464580f0fe0a7811183c361719891 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 14:58:27 -0500 Subject: [PATCH 10/19] Move the creation of the L2 out of the memory base (fix for Ali) and make a wrapper that does it --HG-- extra : convert_revision : 1b878d01667b64be7f5c05faadbf52789bb51616 From 486c44611038b21569c9ab2202c6a0939131a331 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 15:45:53 -0500 Subject: [PATCH 11/19] Remove DUALCPU environment variable and add NUMCPUS, which will build NUMCPUS worth of CPU's. Default is 1 cpu. --HG-- extra : convert_revision : de6adf5a2b2a09eacb099b3904df0c288fd6b33c From 14c461c93c9b83fffb0d629d347a28d4f7b79198 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 15:55:44 -0500 Subject: [PATCH 12/19] Fixed the super/parent change fpr splash2 benchmarks configs/splash2/run.mpy: Change super to parent --HG-- extra : convert_revision : 61d45880b5e334200ebebc24d757c97cbeb048f6 --- configs/splash2/run.mpy | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/splash2/run.mpy b/configs/splash2/run.mpy index a19dcdc939..800bff6f85 100644 --- a/configs/splash2/run.mpy +++ b/configs/splash2/run.mpy @@ -5,12 +5,12 @@ if 'SYSTEM' not in env: if env['SYSTEM'] == 'Simple': from SimpleConfig import * - BaseCPU.workload = Super.workload + BaseCPU.workload = parent.workload SimpleStandAlone.cpu = [ CPU() for i in xrange(int(env['NP'])) ] root = SimpleStandAlone elif env['SYSTEM'] == 'Detailed': from DetailedConfig import * - BaseCPU.workload = Super.workload + BaseCPU.workload = parent.workload DetailedStandAlone.cpu = [ DetailedCPU() for i in xrange(int(env['NP'])) ] root = DetailedStandAlone else: From 9d6fcfd314c3cdabbd3de5219eae4e96058e34df Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 18:18:59 -0500 Subject: [PATCH 13/19] Make the stack size default to 16MB in eio processes --HG-- extra : convert_revision : 1b34b36a8103d091a368917dcbb61c2cc51a471c From f2dd82097263a726888af2a097547f3c6d2d6a03 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Wed, 16 Mar 2005 18:26:32 -0500 Subject: [PATCH 14/19] No need for this ifdef, since the entire process.hh is surounded by an ifndef FULL_SYSTEM --HG-- extra : convert_revision : 81009e5c468eaaee06c83c35f1d05ed2863299a4 --- sim/process.hh | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sim/process.hh b/sim/process.hh index 1c6c6b3fb1..51d7639aca 100644 --- a/sim/process.hh +++ b/sim/process.hh @@ -163,11 +163,7 @@ class Process : public SimObject bool validDataAddr(Addr addr) { return ((data_base <= addr && addr < brk_point) || -#ifdef FULLSYSTEM - ((stack_base - 16*1024*1024) <= addr && addr < stack_base) || -#else (next_thread_stack_base <= addr && addr < stack_base) || -#endif (text_base <= addr && addr < (text_base + text_size)) || (mmap_start <= addr && addr < mmap_end) || (nxm_start <= addr && addr < nxm_end)); From ab5eb7d455f0c1bb0a324f97f442d351b6f0f57b Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 16 Mar 2005 20:32:37 -0500 Subject: [PATCH 15/19] Make panic work in m5.config python/m5/config.py: get panic from the m5 package. --HG-- extra : convert_revision : 0965c13086f5eef7214298227c34cd9693534555 --- python/m5/config.py | 1 + 1 file changed, 1 insertion(+) diff --git a/python/m5/config.py b/python/m5/config.py index e6ad5a0ba5..5da3da19d0 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -27,6 +27,7 @@ from __future__ import generators import os, re, sys, types, inspect +from m5 import panic from convert import * noDot = False From 090301366974386da75fe806a346d3ff953e1e2d Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Mar 2005 23:10:17 -0500 Subject: [PATCH 16/19] Allow proxies to refer to proxies in config files. python/m5/config.py: Allow proxies to refer to other proxies and resolve by recurseivly calling unproxy(). Not sure this works completely (since I don't have any examples to test it on) but it doesn't seem to break any existing config scripts. --HG-- extra : convert_revision : d7fc272d0777d85f89104dfb5d1c5e4d8ddd6d6f --- python/m5/config.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/python/m5/config.py b/python/m5/config.py index e6ad5a0ba5..8e7576c419 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -197,12 +197,13 @@ class Proxy(object): raise AttributeError, \ 'Parent of %s type %s not found at path %s' \ % (base.name, ptype, self._path) - found, done = obj.find(ptype, self._path) - if isinstance(found, Proxy): - done = False + result, done = obj.find(ptype, self._path) obj = obj.parent - return self._mulcheck(found) + if isinstance(result, Proxy): + result = result.unproxy(obj, ptype) + + return self._mulcheck(result) def getindex(obj, index): if index == None: From 5977324255daabfcc6b0e2138f53e27b55a7e21d Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 17 Mar 2005 14:31:08 -0500 Subject: [PATCH 17/19] allow the call to len on Value proxy. --HG-- extra : convert_revision : 1a0aaf8db5ef60e0e7fc053bf4605eb90bb6e9e0 --- python/m5/config.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/python/m5/config.py b/python/m5/config.py index e6ad5a0ba5..bb880cd296 100644 --- a/python/m5/config.py +++ b/python/m5/config.py @@ -895,6 +895,9 @@ class Value(object): def __str__(self): return str(self._getattr()) + def __len__(self): + return len(self._getattr()) + # Regular parameter. class _Param(object): def __init__(self, ptype, *args, **kwargs): From fe764e1276e87bbff6385427355cf08345106284 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 17 Mar 2005 15:32:10 -0500 Subject: [PATCH 18/19] nake systems parameterizable in the number of NICS. appropriately hook up new nibridges and busses for this scenario. --HG-- extra : convert_revision : a6f3f2167300ba695bc4c92a5a9a5648bc897c6a From 3efabb657948e53462bfe60ca93a2ac147074ea1 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 17 Mar 2005 16:08:01 -0500 Subject: [PATCH 19/19] re-implement SplitLIFO so that LIFO now applies to individual sets (LRU-style sets) rather than across the whole partition. --HG-- extra : convert_revision : 684fd9e39f9890181951b8b06f78236c950bf810