Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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@@ -1117,13 +1117,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
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(&cacheData[tid][offset]));
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#if THE_ISA == ALPHA_ISA
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ext_inst = TheISA::makeExtMI(inst, fetch_PC);
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#elif THE_ISA == SPARC_ISA
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ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
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#elif THE_ISA == MIPS_ISA
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ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
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#endif
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//unsigned int result =
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TheISA::predecode(ext_inst, fetch_PC, inst,
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cpu->thread[tid]->getTC());
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// Create a new DynInst from the instruction fetched.
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DynInstPtr instruction = new DynInst(ext_inst,
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@@ -367,18 +367,18 @@ BaseSimpleCPU::preExecute()
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inst = gtoh(inst);
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//If we're not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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#if THE_ISA == ALPHA_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#elif THE_ISA == X86_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#elif THE_ISA == MIPS_ISA
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//Mips doesn't do anything in it's MakeExtMI function right now,
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//so it won't be called.
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StaticInstPtr instPtr = StaticInst::decode(inst);
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#endif
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if (instPtr->isMacroOp()) {
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StaticInstPtr instPtr = NULL;
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//Predecode, ie bundle up an ExtMachInst
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unsigned int result =
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predecode(extMachInst, thread->readPC(), inst, thread->getTC());
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//If an instruction is ready, decode it
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if (result & ExtMIReady)
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instPtr = StaticInst::decode(extMachInst);
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//If we decoded an instruction and it's microcoded, start pulling
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//out micro ops
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if (instPtr && instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->
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fetchMicroOp(thread->readMicroPC());
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@@ -391,17 +391,19 @@ BaseSimpleCPU::preExecute()
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fetchMicroOp(thread->readMicroPC());
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}
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//If we decoded an instruction this "tick", record information about it.
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if(curStaticInst)
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{
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
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curStaticInst->getName(), curStaticInst->getOpcode(),
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curStaticInst->machInst);
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DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
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curStaticInst->getName(), curStaticInst->machInst);
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#if FULL_SYSTEM
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thread->setInst(inst);
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thread->setInst(inst);
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#endif // FULL_SYSTEM
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}
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}
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void
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@@ -74,7 +74,6 @@ namespace Trace {
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class BaseSimpleCPU : public BaseCPU
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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@@ -122,7 +121,10 @@ class BaseSimpleCPU : public BaseCPU
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#endif
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// current instruction
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MachInst inst;
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TheISA::MachInst inst;
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// current extended machine instruction
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TheISA::ExtMachInst extMachInst;
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// Static data storage
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TheISA::LargestRead dataReg;
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@@ -439,9 +439,6 @@ class StaticInst : public StaticInstBase
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//This is defined as inline below.
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static StaticInstPtr decode(ExtMachInst mach_inst);
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/// Return opcode of machine instruction
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uint32_t getOpcode() { return bits(machInst, 31, 26);}
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/// Return name of machine instruction
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std::string getName() { return mnemonic; }
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};
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@@ -474,7 +471,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst>
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/// Construct directly from machine instruction.
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/// Calls StaticInst::decode().
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StaticInstPtr(TheISA::ExtMachInst mach_inst)
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explicit StaticInstPtr(TheISA::ExtMachInst mach_inst)
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: RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
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{
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}
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