diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index d12064720b..ce20e6064b 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -34,6 +34,7 @@
 #include <sstream>
 #include <string>
 
+#include "arch/riscv/insts/bitfields.hh"
 #include "arch/riscv/utility.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
@@ -63,8 +64,15 @@ string LoadReserved::generateDisassembly(Addr pc,
     const SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic;
+    if (AQ || RL)
+        ss << '_';
+    if (AQ)
+        ss << "aq";
+    if (RL)
+        ss << "rl";
+    ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", ("
+            << registerName(RegId(IntRegClass, RS1)) << ')';
     return ss.str();
 }
 
@@ -82,9 +90,16 @@ string StoreCond::generateDisassembly(Addr pc,
     const SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-            << registerName(_srcRegIdx[1]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic;
+    if (AQ || RL)
+        ss << '_';
+    if (AQ)
+        ss << "aq";
+    if (RL)
+        ss << "rl";
+    ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
+            << registerName(RegId(IntRegClass, RS2)) << ", ("
+            << registerName(RegId(IntRegClass, RS1)) << ')';
     return ss.str();
 }
 
@@ -103,9 +118,16 @@ string AtomicMemOp::generateDisassembly(Addr pc,
     const SymbolTable *symtab) const
 {
     stringstream ss;
-    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
-            << registerName(_srcRegIdx[1]) << ", ("
-            << registerName(_srcRegIdx[0]) << ')';
+    ss << mnemonic;
+    if (AQ || RL)
+        ss << '_';
+    if (AQ)
+        ss << "aq";
+    if (RL)
+        ss << "rl";
+    ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
+            << registerName(RegId(IntRegClass, RS2)) << ", ("
+            << registerName(RegId(IntRegClass, RS1)) << ')';
     return ss.str();
 }
 
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh
index eac070e7f2..7b985dc8e1 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -10,4 +10,10 @@
 #define IMMSIGN bits(machInst, 31)
 #define OPCODE  bits(machInst, 6, 0)
 
-#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
+#define AQ      bits(machInst, 26)
+#define RD      bits(machInst, 11, 7)
+#define RL      bits(machInst, 25)
+#define RS1     bits(machInst, 19, 15)
+#define RS2     bits(machInst, 24, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__