diff --git a/tests/configs/gpu-randomtest-ruby.py b/tests/configs/gpu-randomtest-ruby.py
index d0a891880f..3d088f4ecc 100644
--- a/tests/configs/gpu-randomtest-ruby.py
+++ b/tests/configs/gpu-randomtest-ruby.py
@@ -140,6 +140,3 @@ for ruby_port in system.ruby._cpu_ports:
 
 root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
-
-# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 8b92af45c4..9cf92af63f 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -116,6 +116,3 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
 
 root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
-
-# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 27dc0f28c8..207f28c1b8 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -125,6 +125,3 @@ for ruby_port in system.ruby._cpu_ports:
 
 root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
-
-# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 897e053832..248d04654a 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -93,6 +93,3 @@ for (i, cpu) in enumerate(system.cpu):
 
 root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
-
-# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index e76cd3963c..26ca3e9cec 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -97,6 +97,3 @@ cpu.connectAllPorts(system.ruby._cpu_ports[0])
 
 root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
-
-# Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')