diff --git a/include/gem5/asm/generic/m5ops.h b/include/gem5/asm/generic/m5ops.h index f1755961f0..20f38d31f6 100644 --- a/include/gem5/asm/generic/m5ops.h +++ b/include/gem5/asm/generic/m5ops.h @@ -53,6 +53,7 @@ #define M5OP_DEPRECATED3 0x20 // deprecated exit function #define M5OP_EXIT 0x21 #define M5OP_FAIL 0x22 +#define M5OP_SUM 0x23 // For testing #define M5OP_INIT_PARAM 0x30 #define M5OP_LOAD_SYMBOL 0x31 #define M5OP_RESET_STATS 0x40 @@ -90,6 +91,7 @@ M5OP(m5_wake_cpu, M5OP_WAKE_CPU) \ M5OP(m5_exit, M5OP_EXIT) \ M5OP(m5_fail, M5OP_FAIL) \ + M5OP(m5_sum, M5OP_SUM) \ M5OP(m5_init_param, M5OP_INIT_PARAM) \ M5OP(m5_load_symbol, M5OP_LOAD_SYMBOL) \ M5OP(m5_reset_stats, M5OP_RESET_STATS) \ diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h index 3edd4e647a..fddbf534fa 100644 --- a/include/gem5/m5ops.h +++ b/include/gem5/m5ops.h @@ -45,6 +45,9 @@ void m5_wake_cpu(uint64_t cpuid); void m5_exit(uint64_t ns_delay); void m5_fail(uint64_t ns_delay, uint64_t code); +// m5_sum is for sanity checking the gem5 op interface. +unsigned m5_sum(unsigned a, unsigned b, unsigned c, + unsigned d, unsigned e, unsigned f); uint64_t m5_init_param(uint64_t key_str1, uint64_t key_str2); void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period); void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period); diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 4ff54564cf..2730e42d92 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -3031,6 +3031,7 @@ namespace Aarch64 case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); case M5OP_EXIT: return new M5exit64(machInst); case M5OP_FAIL: return new M5fail64(machInst); + case M5OP_SUM: return new M5sum64(machInst); case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); case M5OP_INIT_PARAM: return new Initparam64(machInst); case M5OP_RESET_STATS: return new Resetstats64(machInst); diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa index bbe6649ce8..61206442bc 100644 --- a/src/arch/arm/isa/formats/m5ops.isa +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -52,6 +52,7 @@ def format M5ops() {{ case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); case M5OP_EXIT: return new M5exit(machInst); case M5OP_FAIL: return new M5fail(machInst); + case M5OP_SUM: return new M5sum(machInst); case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); case M5OP_INIT_PARAM: return new Initparam(machInst); case M5OP_RESET_STATS: return new Resetstats(machInst); diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 4bae7a3260..3dcec7ec3c 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -279,6 +279,28 @@ let {{ PseudoInst::loadsymbol(xc->tcBase()); ''' + m5sum_code = ''' + R0 = PseudoInst::m5sum(xc->tcBase(), R0, R1, R2, R3, R4, R5); + ''' + m5sumIop = InstObjParams("m5sum", "M5sum", "PredOp", + { "code": m5sum_code, + "predicate_test": predicateTest }, + ["No_OpClass", "IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5sumIop) + decoder_output += BasicConstructor.subst(m5sumIop) + exec_output += PredOpExecute.subst(m5sumIop) + + m5sum_code64 = ''' + X0 = PseudoInst::m5sum(xc->tcBase(), X0, X1, X2, X3, X4, X5); + ''' + m5sumIop = InstObjParams("m5sum", "M5sum64", "PredOp", + { "code": m5sum_code64, + "predicate_test": predicateTest }, + ["No_OpClass", "IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5sumIop) + decoder_output += BasicConstructor.subst(m5sumIop) + exec_output += PredOpExecute.subst(m5sumIop) + loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", { "code": loadsymbolCode, "predicate_test": predicateTest }, diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index d663ff28d6..e9ee098e6b 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -233,10 +233,14 @@ def operands {{ 'R1': intRegNPC('1'), 'R2': intRegNPC('2'), 'R3': intRegNPC('3'), + 'R4': intRegNPC('4'), + 'R5': intRegNPC('5'), 'X0': intRegX64('0'), 'X1': intRegX64('1'), 'X2': intRegX64('2'), 'X3': intRegX64('3'), + 'X4': intRegX64('4'), + 'X5': intRegX64('5'), # Condition code registers 'CondCodesNZ': ccReg('CCREG_NZ'), diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 3cebad8636..75a4d75785 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -976,6 +976,10 @@ decode OP default Unknown::unknown() 0x21: m5exit({{ PseudoInst::m5exit(xc->tcBase(), O0); }}, No_OpClass, IsNonSpeculative); + 0x23: m5sum({{ + O0 = PseudoInst::m5sum(xc->tcBase(), + O0, O1, O2, O3, O4, O5); + }}, IsNonSpeculative); 0x50: m5readfile({{ O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); }}, IsNonSpeculative); diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 28affdb342..c147d08e4b 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -170,6 +170,10 @@ 0x22: m5fail({{ PseudoInst::m5fail(xc->tcBase(), Rdi, Rsi); }}, IsNonSpeculative); + 0x23: m5sum({{ + Rax = PseudoInst::m5sum(xc->tcBase(), + Rdi, Rsi, Rdx, Rcx, R8, R9); + }}, IsNonSpeculative); 0x30: m5initparam({{ Rax = PseudoInst::initParam(xc->tcBase(), Rdi, Rsi); }}, IsNonSpeculative); diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index be5f62610f..2cd92ddb69 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -112,10 +112,12 @@ def operands {{ 'Rbp': intReg('(INTREG_RBP)', 17), 'Rsi': intReg('(INTREG_RSI)', 18), 'Rdi': intReg('(INTREG_RDI)', 19), - 'FpSrcReg1': floatReg('src1', 20), - 'FpSrcReg2': floatReg('src2', 21), - 'FpDestReg': floatReg('dest', 22), - 'FpData': floatReg('data', 23), + 'R8': intReg('(INTREG_R8)', 20), + 'R9': intReg('(INTREG_R9)', 21), + 'FpSrcReg1': floatReg('src1', 22), + 'FpSrcReg2': floatReg('src2', 23), + 'FpDestReg': floatReg('dest', 24), + 'FpData': floatReg('data', 25), 'RIP': ('PCState', 'uqw', 'pc', (None, None, 'IsControl'), 50), 'NRIP': ('PCState', 'uqw', 'npc', diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index acc9dcf62b..4cbe87ccb5 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -189,6 +189,16 @@ m5exit(ThreadContext *tc, Tick delay) } } +// m5sum is for sanity checking the gem5 op interface. +uint64_t +m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, + uint64_t d, uint64_t e, uint64_t f) +{ + DPRINTF(PseudoInst, "PseudoInst::m5sum(%#x, %#x, %#x, %#x, %#x, %#x)\n", + a, b, c, d, e, f); + return a + b + c + d + e + f; +} + void m5fail(ThreadContext *tc, Tick delay, uint64_t code) { diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 982d6c86b2..8135ee0fcb 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -100,6 +100,8 @@ uint64_t rpns(ThreadContext *tc); void wakeCPU(ThreadContext *tc, uint64_t cpuid); void m5exit(ThreadContext *tc, Tick delay); void m5fail(ThreadContext *tc, Tick delay, uint64_t code); +uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, + uint64_t d, uint64_t e, uint64_t f); void resetstats(ThreadContext *tc, Tick delay, Tick period); void dumpstats(ThreadContext *tc, Tick delay, Tick period); void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); @@ -169,6 +171,11 @@ pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result) invokeSimcall(tc, m5fail); return true; + // M5OP_SUM is for sanity checking the gem5 op interface. + case M5OP_SUM: + result = invokeSimcall(tc, m5sum); + return true; + case M5OP_INIT_PARAM: result = invokeSimcall(tc, initParam); return true;