mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
	<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
	<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
	n = 16
	w = 4
The resulting configuration name is:
	DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

configs/common/MemConfig.py

@@ -152,7 +152,7 @@ def config_mem(options, system):
     them.
     """
 
-    if ( options.mem_type == "HMC_2500_x32"):
+    if ( options.mem_type == "HMC_2500_1x32"):
         HMChost = HMC.config_host_hmc(options, system)
         HMC.config_hmc(options, system, HMChost.hmc_host)
         subsystem = system.hmc_dev
@@ -223,7 +223,7 @@ def config_mem(options, system):
 
     # Connect the controllers to the membus
     for i in xrange(len(subsystem.mem_ctrls)):
-        if (options.mem_type == "HMC_2500_x32"):
+        if (options.mem_type == "HMC_2500_1x32"):
             subsystem.mem_ctrls[i].port = xbar[i/4].master
         else:
             subsystem.mem_ctrls[i].port = xbar.master