From c99d192690f2bd4bd9aec6b6ae717b949c9409ec Mon Sep 17 00:00:00 2001 From: Luming Wang Date: Wed, 24 Nov 2021 12:35:17 +0800 Subject: [PATCH] arch-riscv: fix inUserMode The original inUserMode() simply returns true. However, it should check whether the processor's current privilege level is PRV_U. Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53184 Reviewed-by: Jason Lowe-Power Reviewed-by: Ayaz Akram Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/isa.cc | 5 +++++ src/arch/riscv/isa.hh | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index e26b6faf29..0358889c71 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -205,6 +205,11 @@ ISA::ISA(const Params &p) : BaseISA(p) clear(); } +bool ISA::inUserMode() const +{ + return miscRegFile[MISCREG_PRV] == PRV_U; +} + void ISA::copyRegsFrom(ThreadContext *src) { diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 6435b742e8..143cc698a6 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -98,7 +98,7 @@ class ISA : public BaseISA int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } - bool inUserMode() const override { return true; } + bool inUserMode() const override; void copyRegsFrom(ThreadContext *src) override; void serialize(CheckpointOut &cp) const override;