diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e26b6faf29..0358889c71 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -205,6 +205,11 @@ ISA::ISA(const Params &p) : BaseISA(p)
     clear();
 }
 
+bool ISA::inUserMode() const
+{
+    return miscRegFile[MISCREG_PRV] == PRV_U;
+}
+
 void
 ISA::copyRegsFrom(ThreadContext *src)
 {
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 6435b742e8..143cc698a6 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -98,7 +98,7 @@ class ISA : public BaseISA
     int flattenCCIndex(int reg) const { return reg; }
     int flattenMiscIndex(int reg) const { return reg; }
 
-    bool inUserMode() const override { return true; }
+    bool inUserMode() const override;
     void copyRegsFrom(ThreadContext *src) override;
 
     void serialize(CheckpointOut &cp) const override;