From c9719b44a3ce69b65012ce180142c6014127f718 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Thu, 2 Feb 2023 04:53:50 -0800
Subject: [PATCH] arch-riscv: Implement the resetThread method on the ISA
 object.

This method invokes a Reset fault on the associated ThreadContext.

Change-Id: Ie0725b06e0b506640b9038a986a9c56d9eed7011
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67573
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
---
 src/arch/riscv/isa.cc | 7 +++++++
 src/arch/riscv/isa.hh | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 6e4c380d98..3809c61d63 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -34,6 +34,7 @@
 #include <set>
 #include <sstream>
 
+#include "arch/riscv/faults.hh"
 #include "arch/riscv/interrupts.hh"
 #include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
@@ -723,6 +724,12 @@ ISA::globalClearExclusive()
     tc->getCpuPtr()->wakeup(tc->threadId());
 }
 
+void
+ISA::resetThread()
+{
+    Reset().invoke(tc);
+}
+
 } // namespace RiscvISA
 } // namespace gem5
 
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index e332956972..5a2a610479 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -127,6 +127,8 @@ class ISA : public BaseISA
 
     void globalClearExclusive() override;
 
+    void resetThread() override;
+
     RiscvType rvType() const { return rv_type; }
 };